/******************************************************************************/
/*			  SFR Register Definition			      */
/******************************************************************************/
_sfrbyte   SSCCON  = 0xE8;    /* SSC Control Register			      */
_sfrbyte   STB	   = 0xE9;    /* SSC Transmit Register			      */
_sfrbyte   SRB	   = 0xEA;    /* SSC Receive Register			      */
_sfrbyte   SSCMOD  = 0xEB;    /* SSC Mode Test Register 		      */
_sfrbyte   SCF	   = 0xF8;    /* SSC Status Register			      */
_sfrbyte   SCIEN   = 0xF9;    /* SSC Interrupt Enable Register		      */

_sfrbyte   T2CON   = 0xC8;    /* Timer 2 Control Register		      */
_sfrbyte   TL2	   = 0xCC;    /* Timer 2 Low Byte			      */
_sfrbyte   TH2	   = 0xCD;    /* Timer 2 High Byte			      */
_sfrbyte   RC2L    = 0xCA;    /* Timer 2 Reload/Capture Register, Low Byte    */
_sfrbyte   RC2H    = 0xCB;    /* Timer 2 Reload/Capture Register, High Byte   */

/******************************************************************************/
/*			      SFR Bit Definition			      */
/******************************************************************************/
_sfrbit  BRS0	 = 0xE8;      /* SSC Baudrate Select 0			      */
_sfrbit  BRS1	 = 0xE9;      /* SSC Baudrate Select 1			      */
_sfrbit  BRS2	 = 0xEA;      /* SSC Baudrate Select 2			      */
_sfrbit  CPHA	 = 0xEB;      /* SSC Clock Phase Select 		      */
_sfrbit  CPOL	 = 0xEC;      /* SSC Clock Polarity Control		      */
_sfrbit  MSTR	 = 0xED;      /* SSC Master/Slave Mode Select		      */
_sfrbit  TEN	 = 0xEE;      /* SSC Transmitter Enable 		      */
_sfrbit  SCEN	 = 0xEF;      /* SSC System Enable			      */
_sfrbit  TC	 = 0xF8;      /* SSC Transmit Complete Flag		      */
_sfrbit  WCOL	 = 0xF9;      /* SSC Write Collision Flag		      */