TITLE:            8255 Questions & Answers
    INTEL REF NO:     [7006][MFG_WOL]
    FAXBACK NO:       7006
    PRODUCT COVERED:  8255
    DATE/VERSION:    10/92, Ver 2.00
    RELATED INFO.:    
    KEYWORDS:         8255


8255 & 82C55 Questions and Answers.  Questions refer to both 
versions of component unless otherwise stated.

Q1. Can the port pins on the 82C55 be pulled low when 
    resetting the part?
A1. Yes they may be pulled low.

Q2. What is the number of gates on the 82C55?
A2. There are 5394 gates.

Q3. Can CS# be removed before RD#?
A3. Yes, as long as CS# meets the minimum width requirements.

Q4. What are the ESD limits for the part?
A4. +/- 2000V 

Q5. What does 'Port Pins loaded with more than 20pF may not have
    their logic levels guaranteed, following a hardware reset'?
A5. The Port Pins have weak pull-ups and >20pF could cause the 
    pins to be pulled low or be in an indeterminate state.

Q6. What is the D.C. Spec Idar for?
A6. Ports B & C have Darlington drivers and this value is their
    drive capability.

Q7. What is the max current the I/O Ports can sink (NMOS & CMOS)?
A7. Ports B & C can sink 4.0 mA, CMOS & NMOS. Ports B & C can 
    source 1.7mA for NMOS and 2.5mA for CMOS.  Port A can sink/
    source 1.7mA for the NMOS components, while CMOS devices can
    source/sink 2.5mA through Port A.

Q8. How is the Bit Set/Reset of the mode register used?
A8. When this bit is set low it will internally address the Port
C
    bit Set/Reset register.

Q9. Can the component be read with reset active?
A9. Yes, but the part is placed in Mode 0 with all ports 
    configured as inputs all pins pulled high.  If 
    internal pull-ups are over driven, the pins will read
    as a logic zero.

Q10. What is the difference between the 82C55A and the 82C55A-2?
A10. The A-2 part is faster.

Q11. If the ports A, B & C are programmed as outputs and then 
     port C is programmed as an input will the data in the other
     ports be cleared?
A11. Yes, whenever a new control or mode word is written and
Ports
     A & B are outputs, Ports A & B will be cleared.

Q12. On the NMOS part it is possible to have RD# active and read 
     multiple locations by changing the address.  This does not
     work on the CMOS part, why?
A12. The CMOS part latches the address and CS# on the falling
edge
     of RD# or WR#, while the NMOS part does not.

Q13. When Port A is configured as an output, is it possible to 
     read the output latch?
A13. No, the physical state of the pin will be read.  If Port 
     B or C is used the output latch will be read.

Q14. Part is in noisy environment and outputs are randomly 
     tri-stating, why?
A14. Part is resetting, the component is very noise sensitive and
     will reset.

Q15. How many transistors are there in the 8255A and the 82C55?
A15. The 8255A has 5800 transistors, and the 82C55 has 5200.

Q16. When the 8255 is programmed in mode 0 as an output, can data
be
     read back without reprogramming the chip?
A16. Yes, since each port has slightly different circuitry,
different
     values will be read.  The value read from Port A will
represent
     the physical state of the pins. i.e. if an output port is
tied
     to ground, the value read from Port A will be 00H.  The
values
     read from Ports B & C are different.  These values represent
the
     state of the output latch, not the physical state of the
pins.

Q17. What happens if the strobe line is tied low?
A17. STB# must not go low while IBF is active.  If STB# were to
go low
     when IBF is active, the peripheral will overwrite the
previously
     written data which had not been read by the CPU.  If STB# is
     tied low when initializing the 8255A, the chip will lock up.

Q18. What happens when Ports A, B or C are reset?
A18. By activating a reset, all port outputs are tri-stated.

Q19. By reprogramming one port, what is the effect on the
remaining ports?
A19. Writing to a control word to reprogram one port effects the
operation
     of the other ports, even if that one port is reprogrammed to
exactly
     the same mode.  The effects on each port are mode dependent.
     1.Port A All Modes: Output data is cleared, input is not
cleared.
     2.Port B Mode 0   : Output data is cleared, input is not
cleared.
           Modes 1&2: Both output and input data is cleared.
     3.Port C Mode 0   : Output data is cleared, input is not
cleared.
           Modes 1&2: IBF and INTR are cleared and OBF# is set.
Outputs
                in Port C are not used for handshaking or
                interrupt signals are cleared.  Inputs such as
STB#
                ACK# or'spare' inputs are not effected. The 
                interrupts for Ports A & B are disabled.

Q20. When using the 8255A, pull-up resistors arte used to
stabalize the outputs
     are these needed when using the 82C55.
A20. No, during reset all pins are configured as inputs and are
internally
     pulled to a logic 1.