PROGRAM MEMORY 8051 The 8051 has seperate address spaces for Program Memory and Data Memory. The Program Memory can be up to 64K bytes long. The lower 4K may reside on-chip. Below figure shows a map of the 8051 program memory. 8051 MEMORY FFFF-------------------- FFFF-------------------- | | | | | 60 K | -- | | | BYTES | | | | | EXTERNAL | | | 64 K | | | | | BYTES | 1000-------------------- |- OR -- | EXTERNAL | AND | | | 0FFF-------------------- | | | | 4K BYTES | | | | | INTERNAL | -- | | 0000-------------------- 0000-------------------- PROGRAM MEMORY 8052 The 8052 has seperate address spaces for Program Memory and Data Memory. The Program Memory can be up to 64K bytes long. The lower 8K may reside on-chip. Below figure shows a map of the 8052 program memory. 8052 MEMORY FFFF-------------------- FFFF-------------------- | | | | | 56 K | -- | | | BYTES | | | | | EXTERNAL | | | 64 K | | | | | BYTES | 2000-------------------- |- OR -- | EXTERNAL | AND | | | 1FFF-------------------- | | | | 8K BYTES | | | | | INTERNAL | -- | | 0000-------------------- 0000-------------------- DATA MEMORY 8051 The 8051 can address up to 64K bytes of Data Memory external to the chip. The 'MOVX' instruction is used to access the external data memory. The 8051 has 128 bytes of on-chip RAM plus a number of Special Function Registers (SFR's). The lower 128 bytes of RAM can be accessed either by addressing (MOV data addr) or by indirect addressing (MOV @Ri). INTERNAL FFFF-------------------- | | FF-------------------- | | | SFR's | -- | | | DIRECT | | | | | ADDRESSING | | | 64 K | | ONLY | | | BYTES | 80Ã------------------´ |- AND -- | EXTERNAL | 7F| DIRECT | | | | | & | | | | | INDIRECT | | | | | ADDRESSING | -- | | 00-------------------- 0000-------------------- DATA MEMORY 8052 The 8052 can address up to 64K bytes of Data Memory external to the chip. The 'MOVX' instruction is used to access the external data memory. The 8052 has 256 bytes of on-chip RAM plus a number of Special Function Registers (SFR's). The lower 256 bytes of RAM can be accessed either by addressing (MOV data addr) or by indirect addressing (MOV @Ri). INTERNAL FF----------------- INDIRECT ONLY FFFF-------------------- | | 80h TO FFh | | FF-------------------- | | | | SFR's | | -- | | | DIRECT | | | | | | ADDRESSING | | | | 64 K | | ONLY | -- | | BYTES | 80Ã------------------´ |- AND -- | EXTERNAL | 7F| DIRECT | | | | | & | | | | | INDIRECT | | | | | ADDRESSING | -- | | 00-------------------- 0000-------------------- DIRECT AND INDIRECT ADDRESS AREA The 128 bytes of RAM which can be accessed by both direct and indirect addressing can be divided into 3 segments: 1.Register Banks 0-3: Locations 0 through 1Fh (32 bytes). ASM-51 and the device after reset default to register bank 0. To use the other register banks the user must select them in the software. Each register bank contains 8 one-byte registers, 0 through 7. Reset initializes the Stack Pointer to location 07h and it is incremented once to start from location 08h which is the first register (R0) of the second register bank. Thus, in order to user more than one register bank, the SP should be initialized to a different location of the RAM where it is not used for data storage (ie: higher part of RAM 2.Bit Addressable Area: 16 bytes have been assigned for this segment, 20h-2Fh. Each one of the 128 bits of this segment can be directly addressed (0-7Fh). The bits can be referred to in two ways both of which are acceptable by the ASM-51. One way is to refer to their addressed, ie. 0 to 7Fh. The other way is with reference to bytes 20h to 2Fh. Thus, bits 0-7 can also referred to as bits 20.0-20.7, and bits 8-Fh are the same as 21.0-21.7 and so on. Each of the 16 bytes in this segment can also be addressed as a byte. 3.Scratch Pad Area: Bytes 30h through 7Fh are available to the user as data RAM. However, if the stack pointer has been initialized to this area, enough number of bytes should be left aside to prevent SP data destruction. SPECIAL FUNCTION REGISTERS Symbol Name Address *ACC Accumulator 0E0h *B B Register 0F0h *PSW Program Status Word 0D0h SP Stack Pointer 81h DPTR Data Pointer 2 Bytes à DPL Low Byte 82h - DPH High Byte 83h *P0 Port 0 80h *P1 Port 1 90h *P2 Port 2 0A0h *P3 Port 3 0B0h *IP Interrupt Priority Control 0B8h *IE Interrupt Enable Control 0A8h TMOD Timer/Counter Mode Control 89h *TCON Timer/Counter Control 88h +*T2CON Timer/Counter 2 Control 0C8h TH0 Timer/Counter 0 High Byte 8Ch TL0 Timer/Counter 0 Low Byte 8Ah TH1 Timer/Counter 1 High Byte 8Dh TL1 Timer/Counter 1 Low Byte 8Bh +TH2 Timer/Counter 2 High Byte 0CDh +TL2 Timer/Counter 2 Low Byte 0CCh +RCAP2H Timer/Counter Capture Register High Byte 0CBh +RCAP2L Timer/Counter Capture Register Low Byte 0CAh *SCON Serial Control 98h SBUF Serial Data Buffer 99h PCON Power Control 87h * = Bit addressable + = 8052 only UPL44 FUNCTION CALLS UPL44 has ten BIOS-functions, which are available for the programmer. However you should have this in mind: - The function-number must be given in register R0 - The function returns the values in register A (byte) or DPTR (word) - The function is invoked through the 'CALL 21H' instruction Function-nr. Description Par. GIVE Par. RETURN 00 Reset Program - - 01 Get Character (ASCII) - A 02 Put Character (ASCII) A - 03 Init 8250 - - 04 Init Baudrate A - 05 Get Byte (HEX) - A 06 Put Byte (HEX) A - 07 Convert ASCII to HEX A A 08 Read Jumper Status - A 09 Put String (ASCII) DPTR - ADDRESSES OF THE INDUST44 I/O DEVICES Address (HEX) I/O DEVICE (memory mapped I/O) FF40 PPI-IN Input Register A FF41 PPI-IN Input Register B FF42 PPI-IN Interrupt-Pending Register FF42 PPI-IN Mode Register FF43 PPI-IN Control Register FF48 PPI-OUT Output Register A FF49 PPI-OUT Output Register B FF4A PPI-OUT Mode Register FF4B PPI-OUT Control Register FF50 ACC Transmit-Data Register FF50 ACC Receive-Data Register FF50 ACC Baudrate-Generator Register (divisor low) FF51 ACC Baudrate-Generator Register (divisor high) FF51 ACC Interrupt-Enable Register FF52 ACC Interrupt-Identification Register FF53 ACC Line-Control Register FF54 ACC Modem-Control Register FF55 ACC Line-Status Register FF56 ACC Modem-Status Register FF57 ACC Scratch Pad Register FF58 Timer Counter 0 FF59 Timer Counter 1 FF5A Timer Counter 2 FF5B Timer Control-Word Register FF60-FF67 Dip-Switch 0 FF68-FF6F Dip-Switch 1 FF70-FF77 Dip-Switch 2 FF78-FF7F Dip-Switch 3 FF80 RTC Seconds Register FF81 RTC Seconds Alarm Register FF82 RTC Minutes Register FF83 RTC Minutes Alarm Register FF84 RTC Hours Register FF85 RTC Hours Alarm Register FF87 RTC Day-of-the-Month Register FF88 RTC Month Register FF89 RTC Year Register FF8A RTC Control Register A FF8B RTC Control Register B FF8C RTC Control Register C FF8D RTC Control Register D FF8E-FFBF RTC Battery-Backuped RAM FFFE Configuration Register FFFF Node-Address Register ARITHMETIC OPERATIONS Mnemonic Description Byte Period ADD A,Rn Add register to Acc 1 12 ADD A,direct Add direct byte to Acc 2 12 ADD A,@Ri Add indirect RAM to Acc 1 12 ADD A,#data Add immediate data to Acc 2 12 ADDC A,Rn Add register to Acc with Carry 1 12 ADDC A,direct Add direct byte to Acc with Carry 2 12 ADDC A,@Ri Add indirect RAM to Acc with Carry 1 12 ADDC A,#data Add immediate DATA to Acc with Carry 2 12 SUBB A,Rn Subt. reg. from Acc with borrow 1 12 SUBB A,direct Subt. direct byte from Acc with borrow 2 12 SUBB A,@Ri Subt. indirect RAM from Acc with borrow 1 12 SUBB A,#data Subt. immediate data from Acc with borrow 2 12 INC A Increment Acc 1 12 INC Rn Increment register 1 12 INC direct Increment direct byte 2 12 INC @Ri Increment direct RAM 1 12 DEC A Decrement Acc 1 12 DEC Rn Decrement register 1 12 DEC direct Decrement direct byte 2 12 DEC @Ri Decrement indirect RAM 1 12 INC DPTR Increment Data Pointer 1 24 MUL AB Multiply A & B 1 48 DIV AB Divide A by B 1 48 DA A Decimal Adjust Acc 1 12 BOOLEAN VARIABELE MANIPULATION Mnemonic Description Byte Period CLR C Clear Carry 1 12 CLR bit Clear direct bit 2 12 SETB C Set Carry 1 12 SETB bit Set direct bit 2 12 CPL C Complement Carry 1 12 CPL bit Complement direct bit 2 12 ANL C,bit AND direct bit to Carry 2 24 ANL C,/bit AND complement of direct bit to Carry 2 24 ORL C,bit OR direct bit to Carry 2 24 ORL C,/bit OR complement of direct bit to Carry 2 24 MOV C,bit Move direct bit to Carry 2 12 MOV bit,C Move Carry to direct bit 2 24 JC rel Jump if Carry is set 2 24 JNC rel Jump if Carry is not set 2 24 JB bit,rel Jump if direct bit is set 3 24 JNB bit,rel Jump if direct bit is not set 3 24 JBC bit,rel Jump if direct bit is set and clear bit 3 24 PROGRAM BRANCHING Mnemonic Description Byte Period ACALL addr11 Absolute subroutine call 2 24 LCALL addr16 Long subroutine call 3 24 RET Return from subroutine 1 24 RETI Return from interrupt 1 24 AJMP addr11 Absolute jump 2 24 LJMP addr16 Long jump 3 24 SJMP rel Short jump (relative address) 2 24 JMP @A+DPTR Jump indirect relative to the DPTR 1 24 JZ rel Jump if Acc is zero 2 24 JNZ rel Jump if Acc is not zero 2 24 CJNE A,direct,rel Comp. dir. byte to Acc and jmp if not equal 3 24 CJNE A,#data,rel Comp. immed. to Acc and jmp if not equal 3 24 CJNE Rn,#data,rel Comp. immed. to reg. and jmp if not equal 3 24 CJNE @Ri,#data,rel Comp. immed. to ind. and jmp if not equal 3 24 DJNZ Rn,rel Decrement register and jump if not zero 2 24 DJNZ direct,rel Decrement direct byte and jump if not zero 3 24 NOP No operation 1 12 INDUST44 I/O FUNCTIONS ON PORT 1 Address I/O Device 90h P1.0 LED1 (red) 91h P1.1 LED2 (green) 92h P1.2 Enable Speaker 93h P1.3 Trigger Watchdog Timer 96h P1.6 Enable Transmitters for Bitbus sub-system 97h P1.7 Enable Transmitters for Bitbus sub-system LOGICAL OPERATIONS Mnemonic Description Byte Period ANL A,Rn AND register to Acc 1 12 ANL A,direct AND indirect byte to Acc 2 12 ANL A,@Ri AND indirect RAM into Acc 1 12 ANL A,#data AND immediate data to Acc 2 12 ANL direct,A AND Acc to direct byte 2 12 ANL direct,#data AND immediate data to direct byte 3 24 ORL A,Rn OR register to Acc 1 12 ORL A,direct OR direct byte to Acc 2 12 ORL A,@Ri OR indirect RAM into Acc 1 12 ORL A,#data OR immediate data to Acc 2 12 ORL direct,A OR Acc to direct byte 2 12 ORL direct,#data OR immediate data to direct byte 3 24 XRL A,Rn Exclusive-OR register to Acc 1 12 XRL A,direct Exclusive-OR direct byte to Acc 2 12 XRL A,@Ri Exclusive-OR indirect RAM to Acc 1 12 XRL A,#data Exclusive-OR immediate data to Acc 2 12 XRL direct,A Exclusive-OR Acc to direct byte 2 12 XRL direct,#data Exclusive-OR immediate data to direct byte 3 24 CLR A Clear Acc 1 12 CPL A Complement Acc 1 12 RL A Rotate Acc left 1 12 RLC A Rotate Acc left through the Carry 1 12 RR A Rotate Acc right 1 12 RRC A Rotate Acc right through the Carry 1 12 SWAP A Swap nibbles within the Acc 1 12 DATA TRANSFER Mnemonic Description Byte Period MOV A,Rn Move register to Acc 1 12 MOV A,direct Move direct byte to Acc 2 12 MOV A,@Ri Move indirect RAM to Acc 1 12 MOV A,#data Move immediate data to Acc 2 12 MOV Rn,A Move Acc to register 1 12 MOV Rn,direct Move direct byte to register 2 24 MOV Rn,#data Move immediate data to register 2 12 MOV direct,A Move Acc to direct byte 2 12 MOV direct,Rn Move register to direct byte 2 24 MOV direct,direct Move direct byte to direct byte 3 24 MOV direct,@Ri Move indirect RAM to direct byte 2 24 MOV direct,#data Move immediate data to direct byte 3 24 MOV @Ri,A Move Acc to indirect RAM 1 12 MOV @Ri,direct Move direct byte to indirect RAM 2 24 MOV @Ri,#data Move immediate data to indirect RAM 2 12 MOV DPTR,#data16 Load Data Pointer with a 16-bit constant 3 24 MOVC A,@A+DPTR Move code byte relative to DPTR to Acc 1 24 MOVC A,@A+PC Move code byte relative to PC to Acc 1 24 MOVX A,@Ri Move external RAM (8-bit address) to Acc 1 24 MOVX A,@DPTR Move external RAM (16-bit address) to Acc 1 24 MOVX @Ri,A Move Acc to external RAM (8-bit address) 1 24 MOVX @DPTR,A Move Acc to external RAM (16-bit address) 1 24 PUSH direct Push direct byte onto stack 2 24 POP direct Pop direct byte from stack 2 24 XCH A,Rn Exchange register with Acc 1 12 XCH A,direct Exchange direct byte with Acc 2 12 XCH A,@Ri Exchange indirect RAM with Acc 1 12 XCHD A,@Ri Exchange low-order dgt. to ind. RAM with Acc 1 12 CONTENTS OF SFR'S AFTER POWER-ON OR A RESET Register Value in Binary *ACC 00000000 *B 00000000 *PSW 00000000 SP 00000111 DPTR à DPH 00000000 - DPL 00000000 *P0 11111111 *P1 11111111 *P2 11111111 *P3 11111111 *IP 8051: xxx00000 8052: xx000000 *IE 8051: 0xx00000 8052: 0x000000 TMOD 00000000 *TCON 00000000 +*T2CON 00000000 TH0 00000000 TL0 00000000 TH1 00000000 TL1 00000000 +TH2 00000000 +TL2 00000000 +RCAP2H 00000000 +RCAP2L 00000000 *SCON 00000000 SBUF Indeterminate PCON HMOS: 0xxxxxxx CHMOS: 0xxx0000 x = Undefined * = Bit addressable + = 8052 only PSW: PROGRAM STATUS WORD, BIT ADDRESSABLE ------------------------------------------------- | CY | AC | F0 | RS1 | RS0 | OV | - | P | ------------------------------------------------- CY PSW.7 Carry Flag. AC PSW.6 Auxiliary Carry Flag. F0 PSW.5 Flag 0 available to the user for general purpose. RS1 PSW.4 Register Bank selector bit 1 (see table below). RS0 PSW.3 Register Bank selector bit 2 (see table below). OV PSW.2 Overflow Flag. - PSW.1 User defineable flag. P PWS.0 Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of '1' bits in the Acc. RS1 RS0 Register Bank Address 0 0 0 00h-07h 0 1 1 08h-0Fh 1 0 2 10h-17h 1 1 3 18h-1Fh The value represented by RS0 and RS1 selects the corresponding bank. PCON: POWER CONTROL REGISTER. NOT BIT ADDRESSABLE -------------------------------------------------- | SMOD | - | - | - | GF1 | GF0 | PD | IDL | -------------------------------------------------- SMOD Double baud rate bit. If Timer 1 is used to generate baud rate and SMOD = 1, the baud rate is doubled when the Serial Port is used in modes 1,2 or 3. - Not implemented, reserved for future use. - Not implemented, reserved for future use. - Not implemented, reserved for future use. GF1 General purpose flag bit. GF0 General purpose flag bit. PD Power Down bit. Setting this bit activates Power Down operation in the 80C51BH. (Available only in CHMOS). IDL Idle Mode bit. Setting this bit activates Idle Mode operation in the 80C51BH. (Available only in CHMOS). If '1' are written to bits PD and IDL at the same time, PD takes precedence. IE: INTERRUPT ENABLE REGISTER. BIT ADDRESSABLE ------------------------------------------------- | EA | - | ET2 | ES | ET1 | EX1 | ET0 | EX0 | ------------------------------------------------- If the bit is 0, the corresponding interrupt is disabled. If the bit is 1, the corresponding interrupt is enabled. EA IE.7 Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. - IE.6 Not implemented, reserved for future use. +ET2 IE.5 Enable or disable the Timer 2 overflow or capture interrupt. ES IE.4 Enable or disable the serial port interrupt. ET1 IE.3 Enable or disable the Timer 1 overflow interrupt. EX1 IE.2 Enable or disable External Interrupt 1. ET0 IE.1 Enable or disable the Timer 0 overflow interrupt. EX0 IE.0 Enable or disable External Interrupt 0. + 8052 only IP: INTERRUPT PRIORITY REGISTER. BIT ADDRESSABLE"); ------------------------------------------------- | - | - | PT2 | PS | PT1 | PX1 | PT0 | PX0 | ------------------------------------------------- - IP.7 Not implemented, reserved for future use. - IP.6 Not implemented, reserved for future use. +PT2 IP.5 Defines the Timer 2 interrupt priority level. PS IP.4 Defines the Serial Port interrupt priority level. PT1 IP.3 Defines the Timer 1 interrupt priority level. PX1 IP.2 Defines External Interrupt 1 priority level. PT0 IP.1 Defines the Timer 0 interrupt priority level. PX0 IP.0 Defines the External Interrupt 0 priority level. + 8052 only TCON: TIMER/COUNTER CONTROL REGISTER. BIT ADDRESSABLE 1/2 ------------------------------------------------- | TF1 | TR1 | TF0 | TR0 | IE1 | IT1 | IE0 | IT0 | ------------------------------------------------- TF1 TCON.7 Timer 1 overflow flag. Set by hardware when the Timer/ Counter 1 overflows. Cleared by hardware as processor vectors to the interrupt service routine. TR1 TCON.6 Timer 1 run control bit. Set/cleared by software to turn Timer/Counter 1 ON/OFF. TF0 TCON.5 Timer 0 overflow flag. Set by hardware when the Timer/ Counter 0 overflows. Cleared by hardware as processor vectors to the service routine. TR0 TCON.4 Timer 0 run control bit. Set/cleared by software to turn Timer/Counter 0 ON/OFF. IE1 TCON.3 External Interrupt 1 edge flag. Set by hardware when External Interrupt edge is detected. Cleared by hardware when interrupt is processed. IT1 TCON.2 Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered External Int. IE0 TCON.1 External Interrupt flag. Set by hardware when External Interrupt edge detected. Cleared by hardware when interrupt is processed. IT0 TCON.0 Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered External Interrupt. TMOD: TIMER/COUNTER MODE CONTROL REGISTER, BIT ADDRESSABLE --------------------------------------------------- | GATE | C/T~| M1 | M0 | GATE | C/T~| M1 | M0 | --------------------------------------------------- --------TIMER 1--------- --------TIMER 0--------- GATE When TRx (in TCON) is set and GATE = 1, TIMER/COUNTERx will run only while INTx pin is high (hardware control). When GATE = 0, TIMER/COUNTERx will run only while TRx = 1 (software control). C/T~ Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Counter operation (input from Tx input pin). M1ùM0 Mode selector bit (see table below). M1 M0 Operating Mode 0 0 0 13-bit Timer (MCS-48 compatible) 0 1 1 16-bit Timer/Counter 1 0 2 8-bit Auto-Reload Timer/Counter 1 1 3 (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the Timer 0 control bits. TH0 is an 8-bit Timer, controlled by Timer 1 control bits. 1 1 3 (Timer 1) Timer/Counter 1 stopped. SCON: SERIAL PORT CONTROL REGISTER, BIT ADDRESSABLE 1/2 ------------------------------------------------- | SM0 | SM1 | SM2 | REN | TB8 | RB8 | TI | RI | ------------------------------------------------- SM0 SCON.7 Serial Port mode specifier (see table on next page). SM1 SCON.6 Serial Port mode specifier (see table on next page). SM2 SCON.5 Enables the multiprocessor communications feature in modes 2 & 3. In mode 2 or 3, if SM2 is set to 1 the RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1 the RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be 0. REN SCON.4 Set/Cleared by software to Enable/Disable reception. TB8 SCON.3 The 9th bit that will be transmitted in modes 2 & 3. Set/Cleared by software. RB8 SCON.2 In modes 2 & 3, the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was reveived. In mode 0, RB8 is not used. TI SCON.1 Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes. Must be cleared by software. RI SCON.0 Receive interrupt flag. Set by hardware at the end of the 8th bit timer in mode 0, or halfway through the stop bit in the other modes (except see SM2). Must be cleared by software. SM0 SM1 Mode Description Baud Rate 0 0 0 Shift Register Fosc./12 0 1 1 8-bit UART Variable 1 0 2 9-bit UART Fosc./64 OR Fosc./32 1 1 3 9-bit UART Variable T2CON: TIMER/COUNTER 2 CONTROL REGISTER, BIT ADDRESSABLE ---------------------------------------------------------- | TF2 | EXF2 | RCLK | TCLK | EXEN2 | TR2 | C/T2~| CP/RL2~| ---------------------------------------------------------- 8052 ONLY TF2 T2CON.7 Timer 2 overflow flag set by hardware and cleared by software. TF2 cannot be set when either RCLK = 1 or CLK = 1. EXF2 T2CON.6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX, and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. RCLK T2CON.5 Receive clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its receive clock in modes 1 & 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. TCLK T2CON.4 Transmit clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its transmit clock in modes 1 & 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. EXEN2 T2CON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of negative transition on T2EX if Timer 2 is not being used to clock the Serial Port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 T2CON.2 Software START/STOP control for Timer 2. A logic 1 starts the Timer. C/T2~ T2CON.1 Timer or Counter select. 0 = Internal Timer. 1 = External Event Counter (falling edge triggered). CP/RL2~ T2CON.0 Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, Auto-Reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the Timer is forced to Auto-Reload on Timer 2 overflow.