ERRATA: 8051/31AH SHRINK C-step External Interrupt 0
         
         
         NOTE: This document supersedes all previous 8051/31AH C-step
         External Interrupt 0 Errata.                      
         
         A problem has been found with the External Interrupt 0 (INT0#) on
         the 8051/31AH shrink device, however, there is an easy software
         work around.  Be advised, there are no reliability concerns.  Due
         to the addition of the ALE disable feature on the shrink, appli-
         cations that use Timer1 and External Interrupt 0 can be affected. 
         
         
         
         PRODUCTS AFFECTED:
         
         All 8051/31AH C-step shrink devices regardless of package type or
         temperature range will possess this problem.
         
         Package markings include an indicator in order to differentiate
         between the shrink and non-shrink material.  The 8051AH has an "A"
         marked at the end of the Intel date code (EX.- 0203A Year-1992,
         Week-03).  The 8031AH has an "A" marked at the end of the FPO
         number (EX.-L2031234A).  Therefore, the "A" signifies that the
         device is a shrink part.
         
         
         
         PROBLEM DESCRIPTION:
         
         The SFR that controls the ALE disable function (AUXR) is mapped to
         BYTE address "8EH". The TR1 bit within the TCON register
         is mapped to BIT address "8EH". Byte operations performed on AUXR
         function properly, however, bit instructions performed on TR1 do
         not. During the execution of a bit instruction on TR1 the value of
         TCON.0 (IT0) and AUXR become wire AND'ed with the results written
         into both locations.  If the logic values of TCON.0 and AUXR are
         the same (1x1=1,0x0=0), no corruption occurs.  If the logic values
         are opposite (1x0=0), the resulting 0 value will be written into
         both locations.  This will result in the corruption of either the
         AUXR or TCON.0. The most common symptom of this problem is
         described below.
         
         A. External Interrupt 0 will not work in the falling edge trigger 
            mode under the following conditions:
         
         1. INT0# is setup to be falling edge triggered........TCON.0 = 1
         2. Any bit instruction used on TR1....................TCON.6 = X
         3. ALE disable bit remains at its reset value.........AUXR.0 = 0
              
         
         
         
         






         
         It has been determined that if AUXR.0 = 0,  all bit instructions
         performed on TR1 will cause TCON.0 (IT0) to be cleared.  With
         IT0=0, external interrupt 0 (INT0#) will work as a level triggered
         interrupt instead of the  expected falling edge mode.
         
         SOFTWARE WORK AROUND:
         
         The following are commonly used TR1 bit instructions with their
         equivalent byte instruction replacement :
         
          BIT                     BYTE
         
         SETB TR1  <=====>   ORL TCON,#40H
         CLR TR1   <=====>   ANL TCON,#0BFH
         CPL TR1   <=====>   XRL TCON,#40H
         
         
         Use WEED.EXE program to check existing Rom codes for a bit
         operation on TR1.