The  following list is an explanation of the timing parameters used
    in  the data sheets of the  MCS-51 family of microcontrollers, HMOS
    and CHMOS alike.  These  timing  parameters  are  compared  to  the
    corresponding  parameters   of   the   most   commonly   interfaced
    components, i.e.  latches, EPROMs, RAMs, etc.

    Throughout this text the character  '#'  is  used  to  indicate  an
    active low signal.

    TLHLL--This is the ALE pulse  width,  and  it  corresponds  to  the
    enable pulse  width  (tWL)  of  the  address  latch  device.    The
    interface requires that TLHLL >= tWL.

    TAVLL--This  is the length of time address is valid before ALE goes
    low.   This specification corresponds  to the data  setup time (tS)
    for  the address latch, and TAVLL must  be greater than or equal to
    tS.  (TAVLL >= tS)

    TLLAX--This specifies the amount of  time  that  the  address  will
    remain valid after ALE goes low.  This parameter corresponds to the
    HOLD  time for the address latch (tH).  To satisfy the latch device
    timing spec  TLLAX must be greater than or  equal to tH.  (TLLAX >=
    tH)

    TLLIV--This is the  time that  the controller  will wait  after ALE
    goes  low, before it expects to see the instruction on the bus.  On
    the  EPROMs which have onboard address  latches, the access time is
    given from  ALE low to data valid (tACL).   The value of TLLIV must
    be greater than  or equal  to the  access time.   (TLLIV  >= tACL).
    Also, if  ALE is  used as  the chip  enable signal,  this parameter
    corresponds to  the time from chip select  to output delay (tCE) of
    the EPROM.  Then the requirement is TLLIV >= tCE.

    TLLPL--Time from ALE low to PSEN# low.  This parameter is used with
    memory   devices  which  have  onboard   address  latches.    TLLPL
    corresponds  to the time from chip  select to output enable (tCOE),
    and TLLPL must be greater than or equal to tCOE.  (TLLPL >= tCOE)

    TPLPH--The  duration that PSEN# stays low.  PSEN# is used to enable
    the  external program memory outputs.   Most EPROMs don't specify a
    parameter  for the output enable signal.   However, the tOE (output
    enable to output) implies a minimum value for TPLPH; that is, TPLPH
    must be greater than or equal to tOE.  ( TPLPH >= tOE )

    TPLIV--This  parameter shows  the maximum  time the  controller can
    wait after activating  the PSEN#  (active low)  to receive  a valid
    instruction.  TPLIV corresponds to tOE of the EPROM.  TPLIV must be
    greater than or equal to tOE.  ( TPLIV >= tOE )

    TPXIX--This  is the  time that  the controller  expects to  see the
    instruction remain valid on the bus after PSEN# is no longer valid.
    It  corresponds to tOH (output hold after OE# or CE#) of the EPROM.
    TPXIX must be less than or equal to tOH.  ( TPXIX <= tOH )

    TPXIZ--This defines the  maximum  time  allowable  for  the  memory
    device  to drive the bus  after PSEN# is deactivated.   In order to
    prevent any bus contention, the memory device must float the bus no
    later  than TPXIZ, after PSEN# (the output enable) is not valid any
    more.   TPXIZ corresponds to tDF of  the EPROM, and must be greater
    than or equal to tDF.  ( TPXIZ >= tDF )

    TAVIV--The  maximum length of  time that the  controller will allow
    the  EPROM to  output a  valid instruction  after a  valid address.
    This is the same as tACC in the EPROM.  ( TAVIV - tPROP >= tACC )

    TPLAZ--The amount of time that it will take the controller to float
    the  bus after PSEN# is active, and it  must be less than the tOE of
    the EPROM.  ( TPLAZ < tOE )

    TRLRH--Pulse  width of read (RD#) signal.  Some peripherals require
    a  minimum time for the RD# signal to be active.  An example is the
    programmable  I/O expander (8255A).  TRLRH  must be greater than or
    equal to  tRR which  is the  spec for  the peripheral's  read pulse
    width ( TRLRH >= tRR ).

    TWLWH--Pulse width of write  (WR#) signal.   In  order to  ensure a
    successful  write to the RAM, a minimum pulse width is required for
    the  write signal by the device.   Thus, TWLWH must be greater than
    or equal to tWW of the RAM ( TWLWH >= tWW ).

    TRLDV--This  spec determines how much time the memory system has to
    return  data after the controller drives  the READ line active low.
    This  corresponds to the memory component's tOE output enable spec.
    The tOE time must be less than or equal to TRLDV.  ( TRLDV >= tOE )

    TRHDX--The minimum time  the controller  requires that  data remain
    valid after the READ pin has gone inactive (data hold after RD#).

    TRHDZ--The memory  device must be able to  get the data off (float)
    the bus in time for the CPU  to  drive  the  next  Address  or  bus
    contension may  occur.   This parameter  corresponds to  the memory
    component's tDF.  The tDF value must be less than or equal to TRHDZ
    value.  ( TRHDZ >= tDF )

    TLLDV--This  parameter is associated with  the external data memory
    read and corresponds to the access time of the data memory when ALE
    is used  to drive the chip select pin  of the memory device.  TLLDV
    must  be greater than or  equal to the time  from CS# (chip select)
    low to data valid (tACS).  ( TLLDV >= tACS )


    TLLWL--The time  between ALE going low to  the read or write signal
    going low.   This parameter is  helpful if ALE is  used as the chip
    select signal  to the RAM.  The  corresponding RAM parameter is tCW
    (time of chip select to end of write).  Minimum requirement for the
    interface is TLLWL >= tCW.

    TAVWL--The time between a valid  address  and  the  read  or  write
    signal  going low.  This parameter  corresponds to the tAS (address
    setup time) in the RAM device.  TAVWL must be greater than or equal
    to tAS.  (TAVWL >= tAS)

    TQVWX--This  spec provids information about data setup time for the
    components which  use the negative edge of  the WR# signal to clock
    the data in.  Most RAM devices, however, use the rising edge of the
    WR# signal to latch  the data.   The  parameter that  specifies the
    data setup time for rising edge is TQVWH.

    TQVWH--This spec  provids information  about how  long the  data is
    valid before  the  write  signal  goes  high.    The  corresponding
    parameter  of the RAM device is tDW (data valid to the end of WR#).
    TQVWH must be greater than or equal to tDW.  ( TQVWH >= tDW )



    TWHQX--This specifies  a minimum time  that data is  held after the
    WR# signal  goes high.  The corresponding  parameter of RAM is tDH,
    data hold time after the end of write and, that has to be less than
    or equal to TWHQX.  ( TWHQX >= tDH )

    TRLAZ--In order to prevent  bus  contention,  the  controller  must
    float the  bus bfore  the memory  device drives  it with  the data.
    Most RAM devices do not have a paramter that corresponds to TRLAZ.

    TWHLH--This parameter also is not used by memory devices, but other
    components which share the address data bus may be able to use this
    period.  This time is considered to be dead time for the controller
    and the memory system.