;*****************************************************************************
;*
;* MODULE	: cstartx2.asm
;*
;* DESCRIPTION	: C startup code for C166Sv2.0/Super10 architecture CPU's
;*
;*		- Processor initialization.
;*		- Initialization of static variables in internal or external
;*		  ram is done in '_c_init.asm'.
;*		- Call the user program: main().
;*		- On exit cpu is set in idle mode.
;*
;* COPYRIGHTS	: 2000 TASKING, Inc.
;*
;*****************************************************************************

$CASE
$GENONLY
$DEBUG
$NOLOCALS
$CHECKCPU16
$CHECKBUS18
$NOMOD166			; disable the internal set of SAB 80C166 SFRs
$EXTEND2			; Use C166Sv2.0/Super10 instruction set
@IF( ! @DEFINED(__STDNAMES ) )	
    $STDNAMES(regsuper10bo.def)	@" use C166Sv2.0/Super10 extended set of SFR's (TCONCS0 etc.) by default"
@ELSE
    $STDNAMES(@__STDNAMES)	@"use processor specific register definition "
@ENDI

$include(procdir.asm)		@"Processor specific macro preprocessor directives"
$include(head.asm)
$include(_c_init.asm)		@"initialization of static variables in internal or external ram."
	
	NAME	CSTART		; module name.
	
@IF( @EQS(@MODEL,"LARGE") | @EQS(@MODEL,"SMALL") )
  @IF( @DEFINED( @CALLEINIT))
	EXTERN	@CALLEINIT:FAR		; optional call before EINIT
  @ENDI
  @IF( @DEFINED( @CALLINIT))
	EXTERN	@CALLINIT:FAR		; optional call before _main
  @ENDI
	EXTERN	_main:FAR		; start label user program.
@ELSE
  @IF( @DEFINED( @CALLEINIT))
	EXTERN	@CALLEINIT:NEAR		; optional call before EINIT
  @ENDI
  @IF( @DEFINED( @CALLINIT))
	EXTERN	@CALLINIT:NEAR		; optional call before _main
  @ENDI
	EXTERN	_main:NEAR		; start label user program.
@ENDI

	PUBLIC	__IDLE			; cstart end
	PUBLIC	__EXIT			; address to jump to on 'exit()'.

@IF( @EX_AB )
  @IF( @EQS(@MODEL,"LARGE") | @EQS(@MODEL,"SMALL") )
	EXTERN	_exit:FAR		; exit()
  @ELSE
	EXTERN	_exit:NEAR		; exit()
  @ENDI
@ENDI

@IF( @EQS( @MODEL, "SMALL") | @EQS( @MODEL, "LARGE") )
EXTERN __C_INIT:FAR
@ELSE
EXTERN __C_INIT:NEAR
@ENDI		
@"
	@"Value definitions for Cpu Configuration Register : CPUCON1
@"
	@"Zero Cycle Jump Function (ZCJ) bit: CPUCON1.0
@IF( ! @DEFINED( __ZCJ ) )
	@SET(__ZCJ,1)		@" 0 = Disable Zero Cycle Jump Function
@ENDI				@" 1 = Enable Zero Cycle Jump Function
@"
	@"Branch Prediction Unit (BP) bit: CPUCON1.1
@IF( ! @DEFINED( __BP ) )
	@SET(__BP,1)		@" 0 = Disable Branch Prediction Unit
@ENDI				@" 1 = Enable Branch Prediction Unit
@"
	@"Interruptability of Switch Context Instruction (INTSCXT) bit: CPUCON1.2
@IF( ! @DEFINED( __INTSCXT ) )
	@SET(__INTSCXT,1)	@" 0 = Disable Interruption of SCXT instruction
@ENDI				@" 1 = Enable Interruption of SCXT instruction
@"
	@"Disable Segmentation Control (SGTDIS) bit: CPUCON1.3
@IF( ! @DEFINED( __SGTDIS ) )
	@SET(__SGTDIS,0)	@" 0 = Enable Segmentation
@ENDI				@" 1 = Disable Segmentation
@"
	@"Watchdog Timer Control (WDTCTL) bit: CPUCON1.4
@IF( ! @DEFINED( __WDTCTL ) )
	@SET(__WDTCTL,0)	@" 0 = DISWDT executable until end of EINIT
@ENDI				@" 1 = DISWDT/ENWDT always executable
@"
	@"Vector Table Scaling Factor (VECSC) bitfield: CPUCON1.5-6
@IF( ! @DEFINED( __VECSC ) )
	@SET(__VECSC,0)		@" 0 = Space between two vectors is 2 words
@ENDI				@" 1 = Space between two vectors is 4 words
				@" 2 = Space between two vectors is 8 words
				@" 3 = Space between two vectors is 16 words

	; Process CPUCON1 low byte and high byte values.
@IF( @DEFINED(__EXPERT) * @DEFINED(__CPUCON1) )
	CPC1_L		EQU	(@__CPUCON1)
@ELSE
	CPC1_L  	EQU	((@__VECSC<<5) | (@__WDTCTL<<4) | (@__SGTDIS<<3) | (@__INTSCXT<<2) | (@__BP<<1) | (@__ZCJ))

@ENDI
	CPC1_M_L	EQU	07Fh	; Mask low byte CPUCON1
@"
@"
	@"Value definitions for CPU Configuration Register : CPUCON2
@"
	@"Short Loop Mode (SL) bit: CPUCON2.0
@IF( ! @DEFINED( __SL ) )
	@SET(__SL, 1)		@" 0 = Short Loop mode disabled
@ENDI				@" 1 = Short Loop mode enabled
@"
	@"Fast Pec Event Injection (FASTPEC) bit: CPUCON2.1
@IF( ! @DEFINED( __FASTPEC ) )
	@SET(__FASTPEC, 0)	@" 0 = Direct Injection of PEC Events disabled
@ENDI				@" 1 = Direct Injection of PEC Events enabled
@"
	@"Fast Block Transfer Injection (FASTBL) bit: CPUCON2.2
@IF( ! @DEFINED( __FASTBL ) )
	@SET(__FASTBL, 1)	@" 0 = Direct Injection for Block Transfers disabled
@ENDI				@" 1 = Direct Injection for Block Transfers enabled
@"
	@"Return Stack (RETST) bit: CPUCON2.3
@IF( ! @DEFINED( __RETST ) )
	@SET(__RETST, 1)	@" 0 = Return Stack disabled
@ENDI				@" 1 = Return Stack enabled
@"
	@"Pipeline Bubble Overrun (OVRUN) bit: CPUCON2.4
@IF( ! @DEFINED( __OVRUN ) )
	@SET(__OVRUN, 1)	@" 0 = Overrun of Pipeline Bubbles not allowed
@ENDI				@" 1 = Overrun of Pipeline Bubbles allowed
@"
	@"Zero Cycle Jump Cache (ZSC) bit: CPUCON2.5
@IF( ! @DEFINED( __ZSC ) )
	@SET(__ZSC, 1)		@" 0 = Zero Cycle Jump Cache disabled
@ENDI				@" 1 = Zero Cycle Jump Cache enabled
@"
	@"Stall Instruction (STEN) bit: CPUCON2.6
@IF( ! @DEFINED( __STEN ) )
	@SET(__STEN, 0)		@" 0 = Stall instruction disabled
@ENDI				@" 1 = Stall instruction enabled
@"
	@"Fetch Bypass Control (BYPF) bit: CPUCON2.8
@IF( ! @DEFINED( __BYPF ) )
	@SET(__BYPF, 1)		@" 0 = Bypass Path from Fetch to Decode disabled
@ENDI				@" 1 = Bypass Path from Fetch to Decode enabled
@"
	@"Prefecth Bypass Control (BYPPF) bit: CPUCON2.9
@IF( ! @DEFINED( __BYPPF ) )
	@SET(__BYPPF, 1)	@" 0 = Bypass Path from Prefetch to Decode disabled
@ENDI				@" 1 = Bypass Path from Prefetch to Decode enabled
@"
	@"FIFO Fill Configuration (FIFOFED) bitfield: CPUCON2.10-11
@IF( ! @DEFINED( __FIFOFED ) )
	@SET(__FIFOFED, 3)	@" 0 = FIFO disabled
@ENDI				@" 1 = FIFO filled with up to 1 instruction per cycle
				@" 2 = FIFO filled with up to 2 instructions per cycle
				@" 3 = FIFO filled with up to 3 instructions per cycle
@"
	@"FIFO Depth Configuration (FIFODEPTH) bitfield: CPUCON2.12-15
@IF( ! @DEFINED( __FIFODEPTH ) )
	@SET(__FIFODEPTH, 8)	@" 0 = No FIFO entries (No FIFO)
@ENDI				@" 1 = 1 FIFO entry
				@" ...
				@" 8 = 8 FIFO entries
				@" 9 - 15 = reserved

	; Process CPUCON2 values
@IF( @DEFINED(__EXPERT) * @DEFINED(__CPUCON2) )
	CPC2_H		EQU	(HIGH @__CPUCON2)
	CPC2_L		EQU	(LOW @__CPUCON2)
@ELSE
	CPC2_H		EQU	(@__FIFODEPTH<<4) | (@__FIFOFED<<2) | (@__BYPPF<<1) | (@__BYPF) 
	CPC2_L		EQU	((@__STEN<<6) | (@__ZSC<<5) | (@__OVRUN<<4) | (@__RETST<<3) | (@__FASTBL<<2) | (@__FASTPEC<<1) | (@__SL))
@ENDI
	CPC2_M_H	EQU	0FFh
	CPC2_M_L	EQU	07Fh
@"
@"
	@" Value definitions for System Configuration Register : SYSCON1
@"
	@" Sleep Mode Configuration (SLEEPCON) bitfield: SYSCON1.0-1
@IF( ! @DEFINED( __SLEEPCON ) )
	@SET(__SLEEPCON, 0 )	@" 0 = Normal IDLE mode
@ENDI				@" 1 = SLEEP mode
				@" 2-3 = reserved
@"
	@" Bus Clock Control (BCLKCON) bitfield: SYSCON1.8-11
@IF( ! @DEFINED( __BCLKCON ) )
	@SET(__BCLKCON, 0)	@" 0 = Divider Factor 8 (default)
@ENDI				@" 1 = Divider Factor 1
				@" 2 = Divider Factor 2
				@" 3 = Divider Factor 4
				@" 4-15 = reserved
@"
	@" Port Driver Configuration (PDCFG) bitfield: SYSCON1.2-3
@IF( ! @DEFINED( __SYSC1_PDCFG ) )
	@SET(__SYSC1_PDCFG, 0)	@" 0 = Port drivers are always on
@ENDI				@" 1 = Port drivers are off in SLEEP/IDLE
				@" 2 = Port drivers are off in Powerdown
				@" 3 = Reserved
@"
	@" Program Flash Configuration (PFCFG) bitfield: SYSCON1.4-5
@IF( ! @DEFINED( __SYSC1_PFCFG ) )
	@SET(__SYSC1_PFCFG, 0)	@" 0 = Program Flash is always ON (default)
@ENDI				@" 1 = Program Flash is off in IDLE or Sleep mode
				@" 2-3 = reserved
@"
	@" Clock Prescaler for System (CPSYS) bitfield: SYSCON1.8-10
@IF( ! @DEFINED( __SYSC1_CPSYS ) )
	@SET(__SYSC1_CPSYS, 0)	@" 0 = Divider Factor 1 (default)
@ENDI				@" 1 = Divider Factor 2
				@" 2-7 = reserved
@"
	; Process SYSCON1 values.

@IF( @DEFINED(__EXPERT) * @DEFINED(__SYSCON1) )
	SYSC1_L	  	EQU	(@__SYSCON1)
@ELSE
	SYSC1_L	  	EQU	(((@__BCLKCON | @__SYSC1_CPSYS) <<8) | (@__SYSC1_PFCFG << 4) | (@__SYSC1_PDCFG<<2) | @__SLEEPCON)
@ENDI
@"
@"
	@" Value definitions for System Configuration Register : SYSCON2
@"
	@" Port Output Driver Off Control (DRVOFF) bit: SYSCON2.4
@IF( ! @DEFINED( __DRVOFF ) )
	@SET(__DRVOFF,0)	@" 0 = Port Output Driver state is independant from
@ENDI				@"     sleep and power down mode (default)
				@" 1 = Port output drivers are disabled (high impedance)
				@"     during sleep or power down mode
@"
@"
	; Process SYSCON2 low byte and high byte values.
@IF( @DEFINED(__EXPERT) * @DEFINED(__SYSCON2) )
	SYSC2_L  	EQU	(@__SYSCON2)
@ELSE
	SYSC2_L  	EQU	(@__DRVOFF<<4)
@ENDI
	SYSC2_M_L	EQU	010h
@"
@"
	@" Value definitions for PLL Configuration Register : PLLCON
@"
	@" Output divider PLLODIV:	PLLCON.3-0
@IF( ! @DEFINED( __PLLCON_ODIV ) )
	@SET(__PLLCON_ODIV,7)	@" 7 = Divide by 8
@ENDI
@"
	@" Input divider PLLIDIV:	PLLCON.5-4
@IF( ! @DEFINED( __PLLCON_IDIV ) )
	@SET(__PLLCON_IDIV,1)	@" 1 = Divide by 2
@ENDI
@"
	@" VCO Band Select PLLVB	PLLCON.7-6
@IF( ! @DEFINED( __PLLCON_VB ) )
	@SET(__PLLCON_VB,2)	@" 0 = VCO output frequency 100...150 MHz
@ENDI				@" 1 = VCO output frequency 150...200 MHz
@"				   2 = VCO output frequency 200...250 MHz
@"
	@" Multiplication Factor PLLMUL	PLLCON.12-8
@IF( ! @DEFINED( __PLLCON_MUL ) )
	@SET(__PLLCON_MUL,7)	@" 7 = divide by 8
@ENDI
@"
	@" Operation Control	PLLCTRL	PLLCON.14-13
@IF( ! @DEFINED( __PLLCON_CTRL ) )
	@SET(__PLLCON_CTRL,0)	@" 0 = Bypass PLL clock mult., the PLL is off
@ENDI				@" 1 = Bypass PLL clock mult., the PLL is running
@"				   2 = PLL clock used, input clock switched off
@"				   3 = PLL clock used, input clock connected
@"
@"
	@" Clear Status Flag Trigger PLLCSF	PLLCON.15
@IF( ! @DEFINED( __PLLCON_CSF ) )
	@SET(__PLLCON_CSF,0)	@" 0 = No action (PLLCSF returns to 0 one SCU clock after being set)
@ENDI				@" 1 = The OWD status flags (CLKLOX, CLKHIX in register SYSSTAT) are cleared
@"
@"
	; Process PLLCON values.
@IF( @DEFINED(__EXPERT) * @DEFINED(__PLLCON) )
	PLLC  		EQU	(@__PLLCON)
@ELSE
	PLLC		EQU	((@__PLLCON_CSF << 15) | (@__PLLCON_CTRL << 13) | (@__PLLCON_MUL << 8 ) | (@__PLLCON_VB << 6) | (@__PLLCON_IDIV << 4) | (@__PLLCON_ODIV))
@ENDI
@"
@"
	@" Value definitions for System Configuration Register : SYSCON3
@"
	; Analog/Digital Converter (ADCDIS) enable bit. SYSCON3.0
@IF( ! @DEFINED( __ADCDIS ) )
	@SET(__ADCDIS, 0)	; 0 = Enable ADC convertor
@ENDI				; 1 = Disable ADC convertor
@IF( ! @DEFINED(__SYSCON3_0 ) )
	@SET(__SYSCON3_0, @__ADCDIS)
@ENDI
@"
	@" ASC0 Disable Control (ASC0DIS) bit: SYSCON3.1
@IF( ! @DEFINED( __ASC0DIS ) )
	@SET(__ASC0DIS, 0)	@" 0 = Enable ASC0
@ENDI				@" 1 = Disable ASC0
@IF( ! @DEFINED(__SYSCON3_1 ) )
	@SET(__SYSCON3_1, @__ASC0DIS)
@ENDI
@"
	@" SSC0 Disable Control (SSC0DIS) bit: SYSCON3.2
@IF( ! @DEFINED( __SSCDIS ) )
	@SET(__SSCDIS, 0 )	; 0 = Enable Synchronous Serial Channel SSC
@ENDI				; 1 = Disable Synchronous Serial Channel SSC
@IF( ! @DEFINED(__SYSCON3_2 ) )
	@SET(__SYSCON3_2, @__SSCDIS)
@ENDI
@"
	@" General Purpose Timer Blocks (GPTDIS) enable bit: SYSCON3.3
@IF( ! @DEFINED( __GPTDIS ) )
	@SET(__GPTDIS, 0 )	@" 0 = Enable General Purpose Timer Blocks
@ENDI				@" 1 = Disable General Purpose Timer Blocks
@IF( ! @DEFINED(__SYSCON3_3 ) )
	@SET(__SYSCON3_3, @__GPTDIS)
@ENDI
@"
	@" On-chip (Program) Flash Memory Module (FMDIS/PFMDIS) enable bit. SYSCON3.5
@IF( ! @DEFINED(__SYSCON3_5 ) )
  @IF( @DEFINED( __FMDIS ) )
	@SET(__SYSCON3_5, @__FMDIS )	; 0 = Enable on-chip Flash Memory Module
  @ELSE					; 1 = Disable on-chip Flash Memory Module
	@SET(__SYSCON3_5, 0 )
  @ENDI

  @IF( @DEFINED( __PFMDIS ) )
        @SET(__SYSCON3_5, @__PFMDIS )   ; 0 = Enable on-chip Program Flash Memory Module
  @ENDI                                 ; 1 = Disable on-chip Program Flash Memory Module
@ENDI
@"
	@" CAPCOM Unit 1 (CC1DIS) enable bit. SYSCON3.6
@IF( ! @DEFINED( __CC1DIS ) )
	@SET(__CC1DIS, 0 )	; 0 = Enable CAPCOM Unit 1
@ENDI				; 1 = Disable CAPCOM Unit 1
@IF( ! @DEFINED(__SYSCON3_6 ) )
	@SET(__SYSCON3_6, @__CC1DIS)
@ENDI
@"
	@" CAPCOM Unit 2 (CC2DIS) enable bit. SYSCON3.7
@IF( ! @DEFINED( __CC2DIS ) )
	@SET(__CC2DIS, 0 )	; 0 = Enable CAPCOM Unit 2
@ENDI				; 1 = Disable CAPCOM Unit 2
@IF( ! @DEFINED(__SYSCON3_7 ) )
	@SET(__SYSCON3_7, @__CC2DIS)
@ENDI
@"
	@" PWM Unit (PWMDIS) enable bit. SYSCON3.9
@IF( ! @DEFINED( __PWMDIS ) )
	@SET(__PWMDIS, 0 )	@" 0 = Enable PWM Unit
@ENDI				@" 1 = Disable PWM Unit
@IF( ! @DEFINED(__SYSCON3_9 ) )
	@SET(__SYSCON3_9, @__PWMDIS)
@ENDI
@"
	@" USART ASC1 (ASC1DIS) enable bit. SYSCON3.10
@IF( ! @DEFINED( __ASC1DIS ) )
	@SET(__ASC1DIS, 0)	; 0 = Enable USART ASC1
@ENDI				; 1 = Disable USART ASC1
@IF( ! @DEFINED(__SYSCON3_10 ) )
	@SET(__SYSCON3_10, @__ASC1DIS)
@ENDI
@"
	@" On-chip I2C Bus Module (I2CDIS) enable bit. SYSCON3.11
@IF( ! @DEFINED( __I2CDIS ) )
	@SET(__I2CDIS, 0 )	; 0 = Enable On-chip I2C Bus Module
@ENDI				; 1 = Disable On-chip I2C Bus Module
@IF( ! @DEFINED(__SYSCON3_11 ) )
	@SET(__SYSCON3_11, @__I2CDIS)
@ENDI
@"	
	@" On-chip Serial Data Link Module (SDLMDIS) enable bit. SYSCON3.12
@IF( ! @DEFINED( __SDLMDIS ) )
	@SET(__SDLMDIS, 0 )	; 0 = Enable On-chip SDL Module
@ENDI				; 1 = Disable On-chip SDL Module 
@IF( ! @DEFINED(__SYSCON3_12 ) )
	@SET(__SYSCON3_12, @__SDLMDIS)
@ENDI
@"
	@" On-chip TwinCAN Module (CANDIS) enable bit. SYSCON3.13
@IF( ! @DEFINED( __CANDIS ) )
	@SET(__CANDIS, 0 )	; 0 = Enable On-chip CAN Module 1
@ENDI				; 1 = Disable On-chip CAN Module 1
@IF( ! @DEFINED(__SYSCON3_13 ) )
	@SET(__SYSCON3_13, @__CANDIS)
@ENDI
@"
	@" Synchronous Serial Channel SSC1 (SSC1DIS) enable bit. SYSCON3.15
@IF( ! @DEFINED( __SSC1DIS ) )
	@SET(__SSC1DIS, 0 )	; 0 = Enable Synchronous Serial Channel SSC1
@ENDI				; 1 = Disable Synchronous Serial Channel SSC1
@IF( ! @DEFINED(__SYSCON3_15 ) )
	@SET(__SYSCON3_15, @__SSC1DIS)
@ENDI
@"
	; Process SYSCON3 values.
@IF( @DEFINED(__EXPERT) * @DEFINED(__SYSCON3) )
	SYSC3	  	EQU	(@__SYSCON3)
@ELSE
	SYSC3	  	EQU	((@__SYSCON3_15<<15) | (@__SYSCON3_13<<13) | (@__SYSCON3_12<<12) | (@__SYSCON3_11<<11) | (@__SYSCON3_10<<10) | (@__SYSCON3_9<<9) | (@__SYSCON3_7<<7) | (@__SYSCON3_6<<6) |(@__SYSCON3_5<<5) | (@__SYSCON3_3<<3) |(@__SYSCON3_2<<2) |(@__SYSCON3_1<<1) | @__SYSCON3_0)
@ENDI
	@" Value definitions for EBC Mode 0 register EBCMOD0
@"
	@" Address Pins Enabled (APEN) bitfield: EBCMOD0.0-3
@IF( ! @DEFINED( __APEN ) )
	@SET(__APEN,0)	@" 0 = No address pins enabled
@ENDI			@" 1 = 1 address pin enabled
			@" ...
			@" 8 = 8 address pins enabled
			@" 9-15 = reserved
@"
	@"Chip Select Pins Enabled (CSPEN) bitfiled: EBCMOD.4-7
@IF( ! @DEFINED( __CSPEN ) )
	@SET(__CSPEN,8)	@" 0 = No CS pins enabled
@ENDI			@" 1 = 1 CS pin enabled
			@" ...
			@" 8 = 8 CS pins enabled
			@" 9-15 = reserved
@"
	@"Bus Arbitration Pins Enabled (ARBEN) bit: EBCMOD0.8
@IF( ! @DEFINED( __ARBEN ) )
	@SET(__ARBEN,0)	@" 0 = HOLD, HLDA and BREQ pins are tristate or act as GPIO
@ENDI			@" 1 = HOLD, HLDA and BREQ pins act normally
@"
	@"SLAVE mode enable (SLAVE) bit: EBCMOD0.9
@IF( ! @DEFINED( __SLAVE ) )
	@SET(__SLAVE,0)	@" 0 = Bus arbiter acts in master mode
@ENDI			@" 1 = Bus arbiter acts in slave mode
@"
	@"LEBC pins disable (EBCDIS) bit: EBCMOD0.10
@IF( ! @DEFINED( __EBCDIS ) )
	@SET(__EBCDIS,0) @" 0 = LEBCS is using the pins for external bus
@ENDI			 @" 1 = Pins to be used as GPIO if implemented
@"
	@"Configuration for pins WR/WRL and BHE/WRH (WRCFG) bit: EBCMOD0.11
@IF( ! @DEFINED( __WRCFG ) )
	@SET(__WRCFG,0)	@" 0 = Pins act as WR and BHE
@ENDI			@" 1 = Pins act as WRL and WRH
@"
	@"BHE pin disable (BYTDIS) bit: EBCMOD0.12
@IF( ! @DEFINED( __BYTDIS ) )
	@SET(__BYTDIS,0) @" 0 = BHE enabled
@ENDI			 @" 1 = BHE disabled (GPIO function)
@"
	@"ALE pin disable (ALEDIS) bit: EBCMOD0.13
@IF( ! @DEFINED( __ALEDIS ) )
	@SET(__ALEDIS,0)@" 0 = ALE pin enabled
@ENDI			@" 1 = ALE pin disabled (GPIO function, if implemented)
@"
	@"READY pin disable (RDYDIS) bit: EBCMOD0.14
@IF( ! @DEFINED( __RDYDIS ) )
	@SET(__RDYDIS,0)@" 0 = READY enabled
@ENDI			@" 1 = READY disabled (GPIO function if implemented)
@"
	@"READY pin polarity (RDYPOL) bit: EBCMOD0.15
@IF( ! @DEFINED( __RDYPOL ) )
	@SET(__RDYPOL,0) @" 0 = READY pin is active low
@ENDI			 @" 1 = READY pin is active high

	; Process EBCMOD0 values	
@IF( @DEFINED(__EXPERT) * @DEFINED(__EBCMOD0) )
	EBC0	EQU	(@__EBCMOD0)
@ELSE
	EBC0	EQU	((@__RDYPOL<<15) | (@__RDYDIS<<14) | (@__ALEDIS<<13) | (@__BYTDIS<<12) | (@__WRCFG<<11) | (@__EBCDIS<<10) | (@__SLAVE<<9) | (@__ARBEN<<8) | (@__CSPEN<<4) | (@__APEN))
@ENDI
@"
@"
	@"Value definitions for Function Configuration Register FCONCS0
@"
	@"Enable Chip Select (ENCS0) bit: FCONCS0.0
@IF( ! @DEFINED( __ENCS0 ) )
	@SET(__ENCS0,1)	@" 0 = Chip Select 0 disabled
@ENDI			@" 1 = Chip Select 0 enabled
@"
	@"Ready Enable (RDYEN0) bit: FCONCS0.1
@IF( ! @DEFINED( __RDYEN0 ) )
	@SET(__RDYEN0,0) @" 0 = Access time is controlled by bitfield PHE0
@ENDI			 @" 1 = Access time is controlled by READY signal as well
@"
	@" Ready Mode (RDYMOD0) bit: FCONCS0.2
@IF( ! @DEFINED( __RDYMOD0 ) )
	@SET(__RDYMOD0,0) @" 0 = Asynchronous READY
@ENDI			  @" 1 = Synchronous READY
@"
	@"Bus Type Selection (BTYP0) bitfield: FCONCS0.4-5
@IF( ! @DEFINED( __BTYP0 ) )
	@SET(__BTYP0,3)	@" 0 = 8 bit Demultiplexed bus
@ENDI			@" 1 = 8 bit Multiplexed bus
			@" 2 = 16 bit Demultiplexed bus
			@" 3 = 16 bit Multiplexed bus

	@"Burst mode definition for code fetching FCONCS0.6-7
@IF( ! @DEFINED( __BURST0 ) )
	@SET(__BURST0,0) @" 0 = No Burst Mode
@ENDI			 @" 1 = Synchronous burst or page mode
		         @" 2 = Read controlled synchronous burst mode
			 @" 3 = Reserved

@IF( @__BURST0 == 0 )
	@SET(__ACTIVE_TCONBURSTCS0,0)
@ELSE
	@SET(__ACTIVE_TCONBURSTCS0,1)
@ENDI
	
	; process FCONCS0 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__FCONCS0))
	FCS0		EQU	(@__FCONCS0)
@ELSE
	FCS0		EQU	((@__BURST0<<6) | (@__BTYP0<<4) | (@__RDYMOD0<<2) | (@__RDYEN0<<1) | (@__ENCS0))
@ENDI
@"
	@"Value definitions for Function Configuration Register FCONCS1
@"
	@"Enable Chip Select (ENCS1) bit: FCONCS1.0
@IF( ! @DEFINED( __ENCS1 ) )
	@SET(__ENCS1,0)	@" 0 = Chip Select 1 disabled
@ENDI			@" 1 = Chip Select 1 enabled
@"
	@"Ready Enable (RDYEN1) bit: FCONCS1.1
@IF( ! @DEFINED( __RDYEN1 ) )
	@SET(__RDYEN1,0) @" 0 = Access time is controlled by bitfield PHE1
@ENDI			 @" 1 = Access time is controlled by READY signal as well
@"
	@" Ready Mode (RDYMOD1) bit: FCONCS1.2
@IF( ! @DEFINED( __RDYMOD1 ) )
	@SET(__RDYMOD1,0) @" 0 = Asynchronous READY
@ENDI			  @" 1 = Synchronous READY
@"
	@"Bus Type Selection (BTYP1) bitfield: FCONCS1.4-5
@IF( ! @DEFINED( __BTYP1 ) )
	@SET(__BTYP1,0)	@" 0 = 8 bit Demultiplexed bus
@ENDI			@" 1 = 8 bit Multiplexed bus
			@" 2 = 16 bit Demultiplexed bus
			@" 3 = 16 bit Multiplexed bus

	@"Burst mode definition for code fetching FCONCS1.6-7
@IF( ! @DEFINED( __BURST1 ) )
	@SET(__BURST1,1) @" 0 = No Burst Mode
@ENDI			 @" 1 = Synchronous burst or page mode
		         @" 2 = Read controlled synchronous burst mode
			 @" 3 = Reserved

@IF( @__BURST1 == 0 )
	@SET(__ACTIVE_TCONBURSTCS1,0)
@ELSE
	@SET(__ACTIVE_TCONBURSTCS1,1)
@ENDI

	; process FCONCS1 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__FCONCS1))
	FCS1		EQU	(@__FCONCS1)
@ELSE
	FCS1		EQU	((@__BURST1<<6) | (@__BTYP1<<4) | (@__RDYMOD1<<2) | (@__RDYEN1<<1) | (@__ENCS1))
@ENDI
@"
	@"Value definitions for Function Configuration Register FCONCS2
@"
	@"Enable Chip Select (ENCS2) bit: FCONCS2.0
@IF( ! @DEFINED( __ENCS2 ) )
	@SET(__ENCS2,0)	@" 0 = Chip Select 2 disabled
@ENDI			@" 1 = Chip Select 2 enabled
@"
	@"Ready Enable (RDYEN2) bit: FCONCS2.1
@IF( ! @DEFINED( __RDYEN2 ) )
	@SET(__RDYEN2,0) @" 0 = Access time is controlled by bitfield PHE2
@ENDI			 @" 1 = Access time is controlled by READY signal as well
@"
	@" Ready Mode (RDYMOD2) bit: FCONCS2.2
@IF( ! @DEFINED( __RDYMOD2 ) )
	@SET(__RDYMOD2,0) @" 0 = Asynchronous READY
@ENDI			  @" 1 = Synchronous READY
@"
	@"Bus Type Selection (BTYP2) bitfield: FCONCS2.4-5
@IF( ! @DEFINED( __BTYP2 ) )
	@SET(__BTYP2,0)	@" 0 = 8 bit Demultiplexed bus
@ENDI			@" 1 = 8 bit Multiplexed bus
			@" 2 = 16 bit Demultiplexed bus
			@" 3 = 16 bit Multiplexed bus

	@"Burst mode definition for code fetching FCONCS2.6-7
@IF( ! @DEFINED( __BURST2 ) )
	@SET(__BURST2,0) @" 0 = No Burst Mode
@ENDI			 @" 1 = Synchronous burst or page mode
		         @" 2 = Read controlled synchronous burst mode
			 @" 3 = Reserved

@IF( @__BURST2 == 0 )
	@SET(__ACTIVE_TCONBURSTCS2,0)
@ELSE
	@SET(__ACTIVE_TCONBURSTCS2,1)
@ENDI

	; process FCONCS2 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__FCONCS2))
	FCS2		EQU	(@__FCONCS2)
@ELSE
	FCS2		EQU	((@__BURST2<<6) | (@__BTYP2<<4) | (@__RDYMOD2<<2) | (@__RDYEN2<<1) | (@__ENCS2))
@ENDI
@"
	@"Value definitions for Function Configuration Register FCONCS3
@"
	@"Enable Chip Select (ENCS3) bit: FCONCS3.0
@IF( ! @DEFINED( __ENCS3 ) )
	@SET(__ENCS3,0)	@" 0 = Chip Select 3 disabled
@ENDI			@" 1 = Chip Select 3 enabled
@"
	@"Ready Enable (RDYEN3) bit: FCONCS3.1
@IF( ! @DEFINED( __RDYEN3 ) )
	@SET(__RDYEN3,0) @" 0 = Access time is controlled by bitfield PHE3
@ENDI			 @" 1 = Access time is controlled by READY signal as well
@"
	@" Ready Mode (RDYMOD3) bit: FCONCS3.2
@IF( ! @DEFINED( __RDYMOD3 ) )
	@SET(__RDYMOD3,0) @" 0 = Asynchronous READY
@ENDI			  @" 1 = Synchronous READY
@"
	@"Bus Type Selection (BTYP3) bitfield: FCONCS3.4-5
@IF( ! @DEFINED( __BTYP3 ) )
	@SET(__BTYP3,0)	@" 0 = 8 bit Demultiplexed bus
@ENDI			@" 1 = 8 bit Multiplexed bus
			@" 2 = 16 bit Demultiplexed bus
			@" 3 = 16 bit Multiplexed bus

	@"Burst mode definition for code fetching FCONCS3.6-7
@IF( ! @DEFINED( __BURST3 ) )
	@SET(__BURST3,0) @" 0 = No Burst Mode
@ENDI			 @" 1 = Synchronous burst or page mode
		         @" 2 = Read controlled synchronous burst mode
			 @" 3 = Reserved

@IF( @__BURST3 == 0 )
	@SET(__ACTIVE_TCONBURSTCS3,0)
@ELSE
	@SET(__ACTIVE_TCONBURSTCS3,1)
@ENDI

	; process FCONCS3 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__FCONCS3))
	FCS3		EQU	(@__FCONCS3)
@ELSE
	FCS3		EQU	((@__BURST3<<6) | (@__BTYP3<<4) | (@__RDYMOD3<<2) | (@__RDYEN3<<1) | (@__ENCS3))
@ENDI
@"
	@"Value definitions for Function Configuration Register FCONCS4
@"
	@"Enable Chip Select (ENCS4) bit: FCONCS4.0
@IF( ! @DEFINED( __ENCS4 ) )
	@SET(__ENCS4,0)	@" 0 = Chip Select 4 disabled
@ENDI			@" 1 = Chip Select 4 enabled
@"
	@"Ready Enable (RDYEN4) bit: FCONCS4.1
@IF( ! @DEFINED( __RDYEN4 ) )
	@SET(__RDYEN4,0) @" 0 = Access time is controlled by bitfield PHE4
@ENDI			 @" 1 = Access time is controlled by READY signal as well
@"
	@" Ready Mode (RDYMOD4) bit: FCONCS4.2
@IF( ! @DEFINED( __RDYMOD4 ) )
	@SET(__RDYMOD4,0) @" 0 = Asynchronous READY
@ENDI			  @" 1 = Synchronous READY
@"
	@"Bus Type Selection (BTYP4) bitfield: FCONCS4.4-5
@IF( ! @DEFINED( __BTYP4 ) )
	@SET(__BTYP4,0)	@" 0 = 8 bit Demultiplexed bus
@ENDI			@" 1 = 8 bit Multiplexed bus
			@" 2 = 16 bit Demultiplexed bus
			@" 3 = 16 bit Multiplexed bus

	@"Burst mode definition for code fetching FCONCS4.6-7
@IF( ! @DEFINED( __BURST4 ) )
	@SET(__BURST4,0) @" 0 = No Burst Mode
@ENDI			 @" 1 = Synchronous burst or page mode
		         @" 2 = Read controlled synchronous burst mode
			 @" 3 = Reserved

@IF( @__BURST4 ==  0 )
	@SET(__ACTIVE_TCONBURSTCS4,0)
@ELSE
	@SET(__ACTIVE_TCONBURSTCS4,1)
@ENDI

	; process FCONCS4 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__FCONCS4))
	FCS4		EQU	(@__FCONCS4)
@ELSE
	FCS4		EQU	((@__BURST4<<6) | (@__BTYP4<<4) | (@__RDYMOD4<<2) | (@__RDYEN4<<1) | (@__ENCS4))
@ENDI
@"
	@"Value definitions for Function Configuration Register FCONCS5
@"
	@"Enable Chip Select (ENCS5) bit: FCONCS5.0
@IF( ! @DEFINED( __ENCS5 ) )
	@SET(__ENCS5,0)	@" 0 = Chip Select 5 disabled
@ENDI			@" 1 = Chip Select 5 enabled
@"
	@"Ready Enable (RDYEN5) bit: FCONCS5.1
@IF( ! @DEFINED( __RDYEN5 ) )
	@SET(__RDYEN5,0) @" 0 = Access time is controlled by bitfield PHE5
@ENDI			 @" 1 = Access time is controlled by READY signal as well
@"
	@" Ready Mode (RDYMOD5) bit: FCONCS5.2
@IF( ! @DEFINED( __RDYMOD5 ) )
	@SET(__RDYMOD5,0) @" 0 = Asynchronous READY
@ENDI			  @" 1 = Synchronous READY
@"
	@"Bus Type Selection (BTYP5) bitfield: FCONCS5.4-5
@IF( ! @DEFINED( __BTYP5 ) )
	@SET(__BTYP5,0)	@" 0 = 8 bit Demultiplexed bus
@ENDI			@" 1 = 8 bit Multiplexed bus
			@" 2 = 16 bit Demultiplexed bus
			@" 3 = 16 bit Multiplexed bus

	@"Burst mode definition for code fetching FCONCS5.6-7
@IF( ! @DEFINED( __BURST5 ) )
	@SET(__BURST5,0) @" 0 = No Burst Mode
@ENDI			 @" 1 = Synchronous burst or page mode
		         @" 2 = Read controlled synchronous burst mode
			 @" 3 = Reserved

@IF( @__BURST5 == 0 )
	@SET(__ACTIVE_TCONBURSTCS5,0)
@ELSE
	@SET(__ACTIVE_TCONBURSTCS5,1)
@ENDI

	; process FCONCS5 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__FCONCS5))
	FCS5		EQU	(@__FCONCS5)
@ELSE
	FCS5		EQU	((@__BURST5<<6) | (@__BTYP5<<4) | (@__RDYMOD5<<2) | (@__RDYEN5<<1) | (@__ENCS5))
@ENDI
@"
	@"Value definitions for Function Configuration Register FCONCS6
@"
	@"Enable Chip Select (ENCS6) bit: FCONCS6.0
@IF( ! @DEFINED( __ENCS6 ) )
	@SET(__ENCS6,0)	@" 0 = Chip Select 6 disabled
@ENDI			@" 1 = Chip Select 6 enabled
@"
	@"Ready Enable (RDYEN6) bit: FCONCS6.1
@IF( ! @DEFINED( __RDYEN6 ) )
	@SET(__RDYEN6,0) @" 0 = Access time is controlled by bitfield PHE6
@ENDI			 @" 1 = Access time is controlled by READY signal as well
@"
	@" Ready Mode (RDYMOD6) bit: FCONCS6.2
@IF( ! @DEFINED( __RDYMOD6 ) )
	@SET(__RDYMOD6,0) @" 0 = Asynchronous READY
@ENDI			  @" 1 = Synchronous READY
@"
	@"Bus Type Selection (BTYP6) bitfield: FCONCS6.4-5
@IF( ! @DEFINED( __BTYP6 ) )
	@SET(__BTYP6,0)	@" 0 = 8 bit Demultiplexed bus
@ENDI			@" 1 = 8 bit Multiplexed bus
			@" 2 = 16 bit Demultiplexed bus
			@" 3 = 16 bit Multiplexed bus

	@"Burst mode definition for code fetching FCONCS6.6-7
@IF( ! @DEFINED( __BURST6 ) )
	@SET(__BURST6,0) @" 0 = No Burst Mode
@ENDI			 @" 1 = Synchronous burst or page mode
		         @" 2 = Read controlled synchronous burst mode
			 @" 3 = Reserved

@IF( @__BURST6 == 0 )
	@SET(__ACTIVE_TCONBURSTCS6,0)
@ELSE
	@SET(__ACTIVE_TCONBURSTCS6,1)
@ENDI

	; process FCONCS6 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__FCONCS6))
	FCS6		EQU	(@__FCONCS6)
@ELSE
	FCS6		EQU	((@__BURST6<<6) | (@__BTYP6<<4) | (@__RDYMOD6<<2) | (@__RDYEN6<<1) | (@__ENCS6))
@ENDI
@"
	@"Value definitions for Function Configuration Register FCONCS7
@"
	@"Enable Chip Select (ENCS7) bit: FCONCS7.0
@IF( ! @DEFINED( __ENCS7 ) )
	@SET(__ENCS7,0)	@" 0 = Chip Select 7 disabled
@ENDI			@" 1 = Chip Select 7 enabled
@"
	@"Ready Enable (RDYEN7) bit: FCONCS7.1
@IF( ! @DEFINED( __RDYEN7 ) )
	@SET(__RDYEN7,0) @" 0 = Access time is controlled by bitfield PHE7
@ENDI			 @" 1 = Access time is controlled by READY signal as well
@"
	@" Ready Mode (RDYMOD7) bit: FCONCS7.2
@IF( ! @DEFINED( __RDYMOD7 ) )
	@SET(__RDYMOD7,0) @" 0 = Asynchronous READY
@ENDI			  @" 1 = Synchronous READY
@"
	@"Bus Type Selection (BTYP7) bitfield: FCONCS7.4-5
@IF( ! @DEFINED( __BTYP7 ) )
	@SET(__BTYP7,0)	@" 0 = 8 bit Demultiplexed bus
@ENDI			@" 1 = 8 bit Multiplexed bus
			@" 2 = 16 bit Demultiplexed bus
			@" 3 = 16 bit Multiplexed bus

	@"Burst mode definition for code fetching FCONCS7.6-7
@IF( ! @DEFINED( __BURST7 ) )
	@SET(__BURST7,0) @" 0 = No Burst Mode
@ENDI			 @" 1 = Synchronous burst or page mode
		         @" 2 = Read controlled synchronous burst mode
			 @" 3 = Reserved

@IF( @__BURST7 == 0 )
	@SET(__ACTIVE_TCONBURSTCS7,0)
@ELSE
	@SET(__ACTIVE_TCONBURSTCS7,1)
@ENDI

	; process FCONCS7 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__FCONCS7))
	FCS7		EQU	(@__FCONCS7)
@ELSE
	FCS7		EQU	((@__BURST7<<6) | (@__BTYP7<<4) | (@__RDYMOD7<<2) | (@__RDYEN7<<1) | (@__ENCS7))
@ENDI
@"
@"
	@"Value definitions for the Timing Configuration register: TCONCS0
@"
	@"Phase A clock cycle (PHA0) bitfield: TCONCS0.0-1
@IF( ! @DEFINED( __PHA0 ) )
 	@SET(__PHA0,3)	@" 0 = 0 clock cycles
@ENDI			@" ...
			@" 3 = 3 clock cylcles
@"
	@"Phase B clock cycle (PHB0) bit: TCONCS0.2
@IF( ! @DEFINED( __PHB0 ) )
 	@SET(__PHB0,0)	@" 0 = 1 clock cycle
@ENDI			@" 1 = 2 clock cycles
@"
	@"Phase C clock cycle (PHC0) bitfield: TCONCS0.3-4
@IF( ! @DEFINED( __PHC0 ) )
 	@SET(__PHC0,0)	@" 0 = 0 clock cycles
@ENDI			@" ...
			@" 3 = 3 clock cycles
@"
	@"Phase D clock cycle (PHD0) bitfield: TCONCS0.5
@IF( ! @DEFINED( __PHD0 ) )
 	@SET(__PHD0,0)	@" 0 = 0 clock cycles
@ENDI			@" 1 = 1 clock cycle
@"
	@"Phase E clock cycle (PHE0) bitfield: TCONCS0.6-10
@IF( ! @DEFINED( __PHE0 ) )
 	@SET(__PHE0,9)	@" 0 = 1 clock cycle
@ENDI			@" ...
			@" 31 = 32 clock cycles
@"
	@"Phase F read clock cycle (RDPHF0) bitfield: TCONCS0.11-12
@IF( ! @DEFINED( __RDPHF0 ) )
 	@SET(__RDPHF0,0) @" 0 = 0 clock cycles
@ENDI			 @" ...
			 @" 3 = 3 clock cycles
@"
	@"Phase F write clock cycle (WRPHF0) bitfield: TCONCS0.13-14
@IF( ! @DEFINED( __WRPHF0 ) )
 	@SET(__WRPHF0,3) @" 0 = 0 clock cycles
@ENDI			 @" ...
			 @" 3 = 3 clock cycles

	; Process TCONCS0 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__TCONCS0))
	TCS0		EQU	(@__TCONCS0)
@ELSE
	TCS0	EQU	((@__WRPHF0<<13) | (@__RDPHF0<<11) | (@__PHE0<<6) | (@__PHD0<<5) | (@__PHC0<<3) | (@__PHB0<<2) | (@__PHA0)) & 07FFFh
@ENDI
@"
		@"Value definitions for the Timing Configuration register: TCONCS1
@"
	@"Phase A clock cycle (PHA1) bitfield: TCONCS1.0-1
@IF( ! @DEFINED( __PHA1 ) )
 	@SET(__PHA1,0)	@" 0 = 0 clock cycles
@ENDI			@" ...
			@" 3 = 3 clock cylcles
@"
	@"Phase B clock cycle (PHB1) bit: TCONCS1.2
@IF( ! @DEFINED( __PHB1 ) )
 	@SET(__PHB1,0)	@" 0 = 1 clock cycle
@ENDI			@" 1 = 2 clock cycles
@"
	@"Phase C clock cycle (PHC1) bitfield: TCONCS1.3-4
@IF( ! @DEFINED( __PHC1 ) )
 	@SET(__PHC1,0)	@" 0 = 0 clock cycles
@ENDI			@" ...
			@" 3 = 3 clock cycles
@"
	@"Phase D clock cycle (PHD1) bitfield: TCONCS1.5
@IF( ! @DEFINED( __PHD1 ) )
 	@SET(__PHD1,0)	@" 0 = 0 clock cycles
@ENDI			@" 1 = 1 clock cycle
@"
	@"Phase E clock cycle (PHE1) bitfield: TCONCS1.6-10
@IF( ! @DEFINED( __PHE1 ) )
 	@SET(__PHE1,0)	@" 0 = 1 clock cycle
@ENDI			@" ...
			@" 31 = 32 clock cycles
@"
	@"Phase F read clock cycle (RDPHF1) bitfield: TCONCS1.11-12
@IF( ! @DEFINED( __RDPHF1 ) )
 	@SET(__RDPHF1,0) @" 0 = 0 clock cycles
@ENDI			 @" ...
			 @" 3 = 3 clock cycles
@"
	@"Phase F write clock cycle (WRPHF1) bitfield: TCONCS1.13-14
@IF( ! @DEFINED( __WRPHF1 ) )
 	@SET(__WRPHF1,0) @" 0 = 0 clock cycles
@ENDI			 @" ...
			 @" 3 = 3 clock cycles

	; Process TCONCS1 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__TCONCS1))
	TCS1		EQU	(@__TCONCS1)
@ELSE
	TCS1	EQU	((@__WRPHF1<<13) | (@__RDPHF1<<11) | (@__PHE1<<6) | (@__PHD1<<5) | (@__PHC1<<3) | (@__PHB1<<2) | (@__PHA1)) & 07FFFh
@ENDI
@"
	@"Value definitions for the Timing Configuration register: TCONCS2
@"
	@"Phase A clock cycle (PHA2) bitfield: TCONCS2.0-1
@IF( ! @DEFINED( __PHA2 ) )
 	@SET(__PHA2,0)	@" 0 = 0 clock cycles
@ENDI			@" ...
			@" 3 = 3 clock cylcles
@"
	@"Phase B clock cycle (PHB2) bit: TCONCS2.2
@IF( ! @DEFINED( __PHB2 ) )
 	@SET(__PHB2,0)	@" 0 = 1 clock cycle
@ENDI			@" 1 = 2 clock cycles
@"
	@"Phase C clock cycle (PHC2) bitfield: TCONCS2.3-4
@IF( ! @DEFINED( __PHC2 ) )
 	@SET(__PHC2,0)	@" 0 = 0 clock cycles
@ENDI			@" ...
			@" 3 = 3 clock cycles
@"
	@"Phase D clock cycle (PHD2) bitfield: TCONCS2.5
@IF( ! @DEFINED( __PHD2 ) )
 	@SET(__PHD2,0)	@" 0 = 0 clock cycles
@ENDI			@" 1 = 1 clock cycle
@"
	@"Phase E clock cycle (PHE2) bitfield: TCONCS2.6-10
@IF( ! @DEFINED( __PHE2 ) )
 	@SET(__PHE2,0)	@" 0 = 1 clock cycle
@ENDI			@" ...
			@" 31 = 32 clock cycles
@"
	@"Phase F read clock cycle (RDPHF2) bitfield: TCONCS2.11-12
@IF( ! @DEFINED( __RDPHF2 ) )
 	@SET(__RDPHF2,0) @" 0 = 0 clock cycles
@ENDI			 @" ...
			 @" 3 = 3 clock cycles
@"
	@"Phase F write clock cycle (WRPHF2) bitfield: TCONCS2.13-14
@IF( ! @DEFINED( __WRPHF2 ) )
 	@SET(__WRPHF2,0) @" 0 = 0 clock cycles
@ENDI			 @" ...
			 @" 3 = 3 clock cycles

	; Process TCONCS2 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__TCONCS2))
	TCS2		EQU	(@__TCONCS2)
@ELSE
	TCS2	EQU	((@__WRPHF2<<13) | (@__RDPHF2<<11) | (@__PHE2<<6) | (@__PHD2<<5) | (@__PHC2<<3) | (@__PHB2<<2) | (@__PHA2)) & 07FFFh
@ENDI
@"
	@"Value definitions for the Timing Configuration register: TCONCS3
@"
	@"Phase A clock cycle (PHA3) bitfield: TCONCS3.0-1
@IF( ! @DEFINED( __PHA3 ) )
 	@SET(__PHA3,0)	@" 0 = 0 clock cycles
@ENDI			@" ...
			@" 3 = 3 clock cylcles
@"
	@"Phase B clock cycle (PHB3) bit: TCONCS3.2
@IF( ! @DEFINED( __PHB3 ) )
 	@SET(__PHB3,0)	@" 0 = 1 clock cycle
@ENDI			@" 1 = 2 clock cycles
@"
	@"Phase C clock cycle (PHC3) bitfield: TCONCS3.3-4
@IF( ! @DEFINED( __PHC3 ) )
 	@SET(__PHC3,0)	@" 0 = 0 clock cycles
@ENDI			@" ...
			@" 3 = 3 clock cycles
@"
	@"Phase D clock cycle (PHD3) bitfield: TCONCS3.5
@IF( ! @DEFINED( __PHD3 ) )
 	@SET(__PHD3,0)	@" 0 = 0 clock cycles
@ENDI			@" 1 = 1 clock cycle
@"
	@"Phase E clock cycle (PHE3) bitfield: TCONCS3.6-10
@IF( ! @DEFINED( __PHE3 ) )
 	@SET(__PHE3,0)	@" 0 = 1 clock cycle
@ENDI			@" ...
			@" 31 = 32 clock cycles
@"
	@"Phase F read clock cycle (RDPHF3) bitfield: TCONCS3.11-12
@IF( ! @DEFINED( __RDPHF3 ) )
 	@SET(__RDPHF3,0) @" 0 = 0 clock cycles
@ENDI			 @" ...
			 @" 3 = 3 clock cycles
@"
	@"Phase F write clock cycle (WRPHF3) bitfield: TCONCS3.13-14
@IF( ! @DEFINED( __WRPHF3 ) )
 	@SET(__WRPHF3,0) @" 0 = 0 clock cycles
@ENDI			 @" ...
			 @" 3 = 3 clock cycles

	; Process TCONCS3 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__TCONCS3))
	TCS3		EQU	(@__TCONCS3)
@ELSE
	TCS3	EQU	((@__WRPHF3<<13) | (@__RDPHF3<<11) | (@__PHE3<<6) | (@__PHD3<<5) | (@__PHC3<<3) | (@__PHB3<<2) | (@__PHA3)) & 07FFFh
@ENDI
@"
	@"Value definitions for the Timing Configuration register: TCONCS4
@"
	@"Phase A clock cycle (PHA4) bitfield: TCONCS4.0-1
@IF( ! @DEFINED( __PHA4 ) )
 	@SET(__PHA4,0)	@" 0 = 0 clock cycles
@ENDI			@" ...
			@" 3 = 3 clock cylcles
@"
	@"Phase B clock cycle (PHB4) bit: TCONCS4.2
@IF( ! @DEFINED( __PHB4 ) )
 	@SET(__PHB4,0)	@" 0 = 1 clock cycle
@ENDI			@" 1 = 2 clock cycles
@"
	@"Phase C clock cycle (PHC4) bitfield: TCONCS4.3-4
@IF( ! @DEFINED( __PHC4 ) )
 	@SET(__PHC4,0)	@" 0 = 0 clock cycles
@ENDI			@" ...
			@" 3 = 3 clock cycles
@"
	@"Phase D clock cycle (PHD4) bitfield: TCONCS4.5
@IF( ! @DEFINED( __PHD4 ) )
 	@SET(__PHD4,0)	@" 0 = 0 clock cycles
@ENDI			@" 1 = 1 clock cycle
@"
	@"Phase E clock cycle (PHE4) bitfield: TCONCS4.6-10
@IF( ! @DEFINED( __PHE4 ) )
 	@SET(__PHE4,0)	@" 0 = 1 clock cycle
@ENDI			@" ...
			@" 31 = 32 clock cycles
@"
	@"Phase F read clock cycle (RDPHF4) bitfield: TCONCS4.11-12
@IF( ! @DEFINED( __RDPHF4 ) )
 	@SET(__RDPHF4,0) @" 0 = 0 clock cycles
@ENDI			 @" ...
			 @" 3 = 3 clock cycles
@"
	@"Phase F write clock cycle (WRPHF4) bitfield: TCONCS4.13-14
@IF( ! @DEFINED( __WRPHF4 ) )
 	@SET(__WRPHF4,0) @" 0 = 0 clock cycles
@ENDI			 @" ...
			 @" 3 = 3 clock cycles

	; Process TCONCS4 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__TCONCS4))
	TCS4		EQU	(@__TCONCS4)
@ELSE
	TCS4	EQU	((@__WRPHF4<<13) | (@__RDPHF4<<11) | (@__PHE4<<6) | (@__PHD4<<5) | (@__PHC4<<3) | (@__PHB4<<2) | (@__PHA4)) & 07FFFh
@ENDI
@"
	@"Value definitions for the Timing Configuration register: TCONCS5
@"
	@"Phase A clock cycle (PHA5) bitfield: TCONCS5.0-1
@IF( ! @DEFINED( __PHA5 ) )
 	@SET(__PHA5,0)	@" 0 = 0 clock cycles
@ENDI			@" ...
			@" 3 = 3 clock cylcles
@"
	@"Phase B clock cycle (PHB5) bit: TCONCS5.2
@IF( ! @DEFINED( __PHB5 ) )
 	@SET(__PHB5,0)	@" 0 = 1 clock cycle
@ENDI			@" 1 = 2 clock cycles
@"
	@"Phase C clock cycle (PHC5) bitfield: TCONCS5.3-4
@IF( ! @DEFINED( __PHC5 ) )
 	@SET(__PHC5,0)	@" 0 = 0 clock cycles
@ENDI			@" ...
			@" 3 = 3 clock cycles
@"
	@"Phase D clock cycle (PHD5) bitfield: TCONCS5.5
@IF( ! @DEFINED( __PHD5 ) )
 	@SET(__PHD5,0)	@" 0 = 0 clock cycles
@ENDI			@" 1 = 1 clock cycle
@"
	@"Phase E clock cycle (PHE5) bitfield: TCONCS5.6-10
@IF( ! @DEFINED( __PHE5 ) )
 	@SET(__PHE5,0)	@" 0 = 1 clock cycle
@ENDI			@" ...
			@" 31 = 32 clock cycles
@"
	@"Phase F read clock cycle (RDPHF5) bitfield: TCONCS5.11-12
@IF( ! @DEFINED( __RDPHF5 ) )
 	@SET(__RDPHF5,0) @" 0 = 0 clock cycles
@ENDI			 @" ...
			 @" 3 = 3 clock cycles
@"
	@"Phase F write clock cycle (WRPHF5) bitfield: TCONCS5.13-14
@IF( ! @DEFINED( __WRPHF5 ) )
 	@SET(__WRPHF5,0) @" 0 = 0 clock cycles
@ENDI			 @" ...
			 @" 3 = 3 clock cycles

	; Process TCONCS5 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__TCONCS5))
	TCS5		EQU	(@__TCONCS5)
@ELSE
	TCS5	EQU	((@__WRPHF5<<13) | (@__RDPHF5<<11) | (@__PHE5<<6) | (@__PHD5<<5) | (@__PHC5<<3) | (@__PHB5<<2) | (@__PHA5)) & 07FFFh
@ENDI
@"
	@"Value definitions for the Timing Configuration register: TCONCS6
@"
	@"Phase A clock cycle (PHA6) bitfield: TCONCS6.0-1
@IF( ! @DEFINED( __PHA6 ) )
 	@SET(__PHA6,0)	@" 0 = 0 clock cycles
@ENDI			@" ...
			@" 3 = 3 clock cylcles
@"
	@"Phase B clock cycle (PHB6) bit: TCONCS6.2
@IF( ! @DEFINED( __PHB6 ) )
 	@SET(__PHB6,0)	@" 0 = 1 clock cycle
@ENDI			@" 1 = 2 clock cycles
@"
	@"Phase C clock cycle (PHC6) bitfield: TCONCS6.3-4
@IF( ! @DEFINED( __PHC6 ) )
 	@SET(__PHC6,0)	@" 0 = 0 clock cycles
@ENDI			@" ...
			@" 3 = 3 clock cycles
@"
	@"Phase D clock cycle (PHD6) bitfield: TCONCS6.5
@IF( ! @DEFINED( __PHD6 ) )
 	@SET(__PHD6,0)	@" 0 = 0 clock cycles
@ENDI			@" 1 = 1 clock cycle
@"
	@"Phase E clock cycle (PHE6) bitfield: TCONCS6.6-10
@IF( ! @DEFINED( __PHE6 ) )
 	@SET(__PHE6,0)	@" 0 = 1 clock cycle
@ENDI			@" ...
			@" 31 = 32 clock cycles
@"
	@"Phase F read clock cycle (RDPHF6) bitfield: TCONCS6.11-12
@IF( ! @DEFINED( __RDPHF6 ) )
 	@SET(__RDPHF6,0) @" 0 = 0 clock cycles
@ENDI			 @" ...
			 @" 3 = 3 clock cycles
@"
	@"Phase F write clock cycle (WRPHF6) bitfield: TCONCS6.13-14
@IF( ! @DEFINED( __WRPHF6 ) )
 	@SET(__WRPHF6,0) @" 0 = 0 clock cycles
@ENDI			 @" ...
			 @" 3 = 3 clock cycles

	; Process TCONCS6 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__TCONCS6))
	TCS6		EQU	(@__TCONCS6)
@ELSE
	TCS6	EQU	((@__WRPHF6<<13) | (@__RDPHF6<<11) | (@__PHE6<<6) | (@__PHD6<<5) | (@__PHC6<<3) | (@__PHB6<<2) | (@__PHA6)) & 07FFFh
@ENDI
@"
	@"Value definitions for the Timing Configuration register: TCONCS7
@"
	@"Phase A clock cycle (PHA7) bitfield: TCONCS7.0-1
@IF( ! @DEFINED( __PHA7 ) )
 	@SET(__PHA7,0)	@" 0 = 0 clock cycles
@ENDI			@" ...
			@" 3 = 3 clock cylcles
@"
	@"Phase B clock cycle (PHB7) bit: TCONCS7.2
@IF( ! @DEFINED( __PHB7 ) )
 	@SET(__PHB7,0)	@" 0 = 1 clock cycle
@ENDI			@" 1 = 2 clock cycles
@"
	@"Phase C clock cycle (PHC7) bitfield: TCONCS7.3-4
@IF( ! @DEFINED( __PHC7 ) )
 	@SET(__PHC7,0)	@" 0 = 0 clock cycles
@ENDI			@" ...
			@" 3 = 3 clock cycles
@"
	@"Phase D clock cycle (PHD7) bitfield: TCONCS7.5
@IF( ! @DEFINED( __PHD7 ) )
 	@SET(__PHD7,0)	@" 0 = 0 clock cycles
@ENDI			@" 1 = 1 clock cycle
@"
	@"Phase E clock cycle (PHE7) bitfield: TCONCS7.6-10
@IF( ! @DEFINED( __PHE7 ) )
 	@SET(__PHE7,0)	@" 0 = 1 clock cycle
@ENDI			@" ...
			@" 31 = 32 clock cycles
@"
	@"Phase F read clock cycle (RDPHF7) bitfield: TCONCS7.11-12
@IF( ! @DEFINED( __RDPHF7 ) )
 	@SET(__RDPHF7,0) @" 0 = 0 clock cycles
@ENDI			 @" ...
			 @" 3 = 3 clock cycles
@"
	@"Phase F write clock cycle (WRPHF7) bitfield: TCONCS7.13-14
@IF( ! @DEFINED( __WRPHF7 ) )
 	@SET(__WRPHF7,0) @" 0 = 0 clock cycles
@ENDI			 @" ...
			 @" 3 = 3 clock cycles

	; Process TCONCS7 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__TCONCS7))
	TCS7		EQU	(@__TCONCS7)
@ELSE
	TCS7	EQU	((@__WRPHF7<<13) | (@__RDPHF7<<11) | (@__PHE7<<6) | (@__PHD7<<5) | (@__PHC7<<3) | (@__PHB7<<2) | (@__PHA7)) & 07FFFh
@ENDI
@"
	@"Value definitions for Address Select register: ADDRSEL1
@"
	@"Address Range Size selection (RGSZ1) bitfield: ADDRSEL1.0-3
@IF( ! @DEFINED( __RGSZ1 ) )
	@SET(__RGSZ1,0)	@" 0 = 4 Kb
@ENDI			@" 1 = 8 Kb
			@" 2 = 16 Kb
			@" 3 = 32 Kb
			@" 4 = 64 Kb
			@" 5 = 128 Kb
			@" 6 = 256 Kb
			@" 7 = 512 Kb
			@" 8 = 1 Mb
			@" 9 = 2 Mb
			@" 10 = 4 Mb
			@" 11 = 8 Mb
			@" 12 - 15 = reserved
@"
	@" Address Range Start Address Selection (RGSAD1) bitfield: ADDRSEL1.4-15
@IF( ! @DEFINED( __RGSAD1 ) )
	@SET(__RGSAD1, 0) @" Defines upper bits of start address
@ENDI

 	; Process ADDRSEL1 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__ADDRSEL1))
	ADRS1		EQU	(@__ADDRSEL1)
@ELSE
	ADRS1	EQU	((@__RGSAD1<<4) | (@__RGSZ1))
@ENDI
@"
	@"Value definitions for Address Select register: ADDRSEL2
@"
	@"Address Range Size selection (RGSZ2) bitfield: ADDRSEL2.0-3
@IF( ! @DEFINED( __RGSZ2 ) )
	@SET(__RGSZ2,0)	@" 0 = 4 Kb
@ENDI			@" 1 = 8 Kb
			@" 2 = 16 Kb
			@" 3 = 32 Kb
			@" 4 = 64 Kb
			@" 5 = 128 Kb
			@" 6 = 256 Kb
			@" 7 = 512 Kb
			@" 8 = 1 Mb
			@" 9 = 2 Mb
			@" 10 = 4 Mb
			@" 11 = 8 Mb
			@" 12 - 15 = reserved
@"
	@" Address Range Start Address Selection (RGSAD2) bitfield: ADDRSEL2.4-15
@IF( ! @DEFINED( __RGSAD2 ) )
	@SET(__RGSAD2, 0) @" Defines upper bits of start address
@ENDI

 	; Process ADDRSEL2 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__ADDRSEL2))
	ADRS2		EQU	(@__ADDRSEL2)
@ELSE
	ADRS2	EQU	((@__RGSAD2<<4) | (@__RGSZ2))
@ENDI
@"
	@"Value definitions for Address Select register: ADDRSEL3
@"
	@"Address Range Size selection (RGSZ3) bitfield: ADDRSEL3.0-3
@IF( ! @DEFINED( __RGSZ3 ) )
	@SET(__RGSZ3,0)	@" 0 = 4 Kb
@ENDI			@" 1 = 8 Kb
			@" 2 = 16 Kb
			@" 3 = 32 Kb
			@" 4 = 64 Kb
			@" 5 = 128 Kb
			@" 6 = 256 Kb
			@" 7 = 512 Kb
			@" 8 = 1 Mb
			@" 9 = 2 Mb
			@" 10 = 4 Mb
			@" 11 = 8 Mb
			@" 12 - 15 = reserved
@"
	@" Address Range Start Address Selection (RGSAD3) bitfield: ADDRSEL3.4-15
@IF( ! @DEFINED( __RGSAD3 ) )
	@SET(__RGSAD3, 0) @" Defines upper bits of start address
@ENDI

 	; Process ADDRSEL3 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__ADDRSEL3))
	ADRS3		EQU	(@__ADDRSEL3)
@ELSE
	ADRS3	EQU	((@__RGSAD3<<4) | (@__RGSZ3))
@ENDI
@"
	@"Value definitions for Address Select register: ADDRSEL4
@"
	@"Address Range Size selection (RGSZ4) bitfield: ADDRSEL4.0-3
@IF( ! @DEFINED( __RGSZ4 ) )
	@SET(__RGSZ4,0)	@" 0 = 4 Kb
@ENDI			@" 1 = 8 Kb
			@" 2 = 16 Kb
			@" 3 = 32 Kb
			@" 4 = 64 Kb
			@" 5 = 128 Kb
			@" 6 = 256 Kb
			@" 7 = 512 Kb
			@" 8 = 1 Mb
			@" 9 = 2 Mb
			@" 10 = 4 Mb
			@" 11 = 8 Mb
			@" 12 - 15 = reserved
@"
	@" Address Range Start Address Selection (RGSAD4) bitfield: ADDRSEL4.4-15
@IF( ! @DEFINED( __RGSAD4 ) )
	@SET(__RGSAD4, 0) @" Defines upper bits of start address
@ENDI

 	; Process ADDRSEL4 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__ADDRSEL4))
	ADRS4		EQU	(@__ADDRSEL4)
@ELSE
	ADRS4	EQU	((@__RGSAD4<<4) | (@__RGSZ4))
@ENDI
@"
	@"Value definitions for Address Select register: ADDRSEL5
@"
	@"Address Range Size selection (RGSZ5) bitfield: ADDRSEL5.0-3
@IF( ! @DEFINED( __RGSZ5 ) )
	@SET(__RGSZ5,0)	@" 0 = 4 Kb
@ENDI			@" 1 = 8 Kb
			@" 2 = 16 Kb
			@" 3 = 32 Kb
			@" 4 = 64 Kb
			@" 5 = 128 Kb
			@" 6 = 256 Kb
			@" 7 = 512 Kb
			@" 8 = 1 Mb
			@" 9 = 2 Mb
			@" 10 = 4 Mb
			@" 11 = 8 Mb
			@" 12 - 15 = reserved
@"
	@" Address Range Start Address Selection (RGSAD5) bitfield: ADDRSEL5.4-15
@IF( ! @DEFINED( __RGSAD5 ) )
	@SET(__RGSAD5, 0) @" Defines upper bits of start address
@ENDI

 	; Process ADDRSEL5 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__ADDRSEL5))
	ADRS5		EQU	(@__ADDRSEL5)
@ELSE
	ADRS5	EQU	((@__RGSAD5<<4) | (@__RGSZ5))
@ENDI
@"
	@"Value definitions for Address Select register: ADDRSEL6
@"
	@"Address Range Size selection (RGSZ6) bitfield: ADDRSEL6.0-3
@IF( ! @DEFINED( __RGSZ6 ) )
	@SET(__RGSZ6,0)	@" 0 = 4 Kb
@ENDI			@" 1 = 8 Kb
			@" 2 = 16 Kb
			@" 3 = 32 Kb
			@" 4 = 64 Kb
			@" 5 = 128 Kb
			@" 6 = 256 Kb
			@" 7 = 512 Kb
			@" 8 = 1 Mb
			@" 9 = 2 Mb
			@" 10 = 4 Mb
			@" 11 = 8 Mb
			@" 12 - 15 = reserved
@"
	@" Address Range Start Address Selection (RGSAD6) bitfield: ADDRSEL6.4-15
@IF( ! @DEFINED( __RGSAD6 ) )
	@SET(__RGSAD6, 0) @" Defines upper bits of start address
@ENDI

 	; Process ADDRSEL6 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__ADDRSEL6))
	ADRS6		EQU	(@__ADDRSEL6)
@ELSE
	ADRS6	EQU	((@__RGSAD6<<4) | (@__RGSZ6))
@ENDI
@"
	@"Value definitions for Address Select register: ADDRSEL7
@"
	@"Address Range Size selection (RGSZ7) bitfield: ADDRSEL7.0-3
@IF( ! @DEFINED( __RGSZ7 ) )
	@SET(__RGSZ7,0)	@" 0 = 4 Kb
@ENDI			@" 1 = 8 Kb
			@" 2 = 16 Kb
			@" 3 = 32 Kb
			@" 4 = 64 Kb
			@" 5 = 128 Kb
			@" 6 = 256 Kb
			@" 7 = 512 Kb
			@" 8 = 1 Mb
			@" 9 = 2 Mb
			@" 10 = 4 Mb
			@" 11 = 8 Mb
			@" 12 - 15 = reserved
@"
	@" Address Range Start Address Selection (RGSAD7) bitfield: ADDRSEL7.4-15
@IF( ! @DEFINED( __RGSAD7 ) )
	@SET(__RGSAD7, 0) @" Defines upper bits of start address
@ENDI

 	; Process ADDRSEL7 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__ADDRSEL7))
	ADRS7		EQU	(@__ADDRSEL7)
@ELSE
	ADRS7	EQU	((@__RGSAD7<<4) | (@__RGSZ7))
@ENDI
@"
@"
	@"Value definitions for Additional Timing for Chip Select 0 Register: TCONBURSTCS0
@"
	@"Phase EB low bitfield: TCONBURSTCS0.0-3
@IF( ! @DEFINED( __BURST0_PHEBL ) )
	@SET(__BURST0_PHEBL,0) @" clock cycles
@ENDI
@"
	@"Phase EB high bitfield: TCONBURSTCS0.4-7
@IF( ! @DEFINED( __BURST0_PHEBH ) )
	@SET(__BURST0_PHEBH,0) @" clock cycles
@ENDI
@"
	; Process TCONBURSTCS0 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__TCONBURSTCS0))
	TCBURST0	EQU	(@__TCONBURSTCS0)
@ELSE
	TCBURST0	EQU	((@__BURST0_PHEBH<<4) | (@__BURST0_PHEBL))
@ENDI
@"
@"
	@"Value definitions for Additional Timing for Chip Select 1 Register: TCONBURSTCS1
@"
	@"Phase EB low bitfield: TCONBURSTCS1.0-3
@IF( ! @DEFINED( __BURST1_PHEBL ) )
	@SET(__BURST1_PHEBL,0) @" clock cycles
@ENDI
@"
	@"Phase EB high bitfield: TCONBURSTCS1.4-7
@IF( ! @DEFINED( __BURST1_PHEBH ) )
	@SET(__BURST1_PHEBH,0) @" clock cycles
@ENDI
@"
	; Process TCONBURSTCS1 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__TCONBURSTCS1))
	TCBURST1	EQU	(@__TCONBURSTCS1)
@ELSE
	TCBURST1	EQU	((@__BURST1_PHEBH<<4) | (@__BURST1_PHEBL))
@ENDI
@"
@"
	@"Value definitions for Additional Timing for Chip Select 2 Register: TCONBURSTCS2
@"
	@"Phase EB low bitfield: TCONBURSTCS2.0-3
@IF( ! @DEFINED( __BURST2_PHEBL ) )
	@SET(__BURST2_PHEBL,0) @" clock cycles
@ENDI
@"
	@"Phase EB high bitfield: TCONBURSTCS2.4-7
@IF( ! @DEFINED( __BURST2_PHEBH ) )
	@SET(__BURST2_PHEBH,0) @" clock cycles
@ENDI
@"
	; Process TCONBURSTCS2 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__TCONBURSTCS2))
	TCBURST2	EQU	(@__TCONBURSTCS2)
@ELSE
	TCBURST2	EQU	((@__BURST2_PHEBH<<4) | (@__BURST2_PHEBL))
@ENDI
@"
@"
	@"Value definitions for Additional Timing for Chip Select 3 Register: TCONBURSTCS3
@"
	@"Phase EB low bitfield: TCONBURSTCS3.0-3
@IF( ! @DEFINED( __BURST3_PHEBL ) )
	@SET(__BURST3_PHEBL,0) @" clock cycles
@ENDI
@"
	@"Phase EB high bitfield: TCONBURSTCS3.4-7
@IF( ! @DEFINED( __BURST3_PHEBH ) )
	@SET(__BURST3_PHEBH,0) @" clock cycles
@ENDI
@"
	; Process TCONBURSTCS3 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__TCONBURSTCS3))
	TCBURST3	EQU	(@__TCONBURSTCS3)
@ELSE
	TCBURST3	EQU	((@__BURST3_PHEBH<<4) | (@__BURST3_PHEBL))
@ENDI
@"
@"
	@"Value definitions for Additional Timing for Chip Select 4 Register: TCONBURSTCS4
@"
	@"Phase EB low bitfield: TCONBURSTCS4.0-3
@IF( ! @DEFINED( __BURST4_PHEBL ) )
	@SET(__BURST4_PHEBL,0) @" clock cycles
@ENDI
@"
	@"Phase EB high bitfield: TCONBURSTCS4.4-7
@IF( ! @DEFINED( __BURST4_PHEBH ) )
	@SET(__BURST4_PHEBH,0) @" clock cycles
@ENDI
@"
	; Process TCONBURSTCS4 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__TCONBURSTCS4))
	TCBURST4	EQU	(@__TCONBURSTCS4)
@ELSE
	TCBURST4	EQU	((@__BURST4_PHEBH<<4) | (@__BURST4_PHEBL))
@ENDI
@"
@"
	@"Value definitions for Additional Timing for Chip Select 5 Register: TCONBURSTCS5
@"
	@"Phase EB low bitfield: TCONBURSTCS5.0-3
@IF( ! @DEFINED( __BURST5_PHEBL ) )
	@SET(__BURST5_PHEBL,0) @" clock cycles
@ENDI
@"
	@"Phase EB high bitfield: TCONBURSTCS5.4-7
@IF( ! @DEFINED( __BURST5_PHEBH ) )
	@SET(__BURST5_PHEBH,0) @" clock cycles
@ENDI
@"
	; Process TCONBURSTCS5 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__TCONBURSTCS5))
	TCBURST5	EQU	(@__TCONBURSTCS5)
@ELSE
	TCBURST5	EQU	((@__BURST5_PHEBH<<4) | (@__BURST5_PHEBL))
@ENDI
@"
@"
	@"Value definitions for Additional Timing for Chip Select 6 Register: TCONBURSTCS6
@"
	@"Phase EB low bitfield: TCONBURSTCS6.0-3
@IF( ! @DEFINED( __BURST6_PHEBL ) )
	@SET(__BURST6_PHEBL,0) @" clock cycles
@ENDI
@"
	@"Phase EB high bitfield: TCONBURSTCS6.4-7
@IF( ! @DEFINED( __BURST6_PHEBH ) )
	@SET(__BURST6_PHEBH,0) @" clock cycles
@ENDI
@"
	; Process TCONBURSTCS6 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__TCONBURSTCS6))
	TCBURST6	EQU	(@__TCONBURSTCS6)
@ELSE
	TCBURST6	EQU	((@__BURST6_PHEBH<<4) | (@__BURST6_PHEBL))
@ENDI
@"
@"
	@"Value definitions for Additional Timing for Chip Select 7 Register: TCONBURSTCS7
@"
	@"Phase EB low bitfield: TCONBURSTCS7.0-3
@IF( ! @DEFINED( __BURST7_PHEBL ) )
	@SET(__BURST7_PHEBL,0) @" clock cycles
@ENDI
@"
	@"Phase EB high bitfield: TCONBURSTCS7.4-7
@IF( ! @DEFINED( __BURST7_PHEBH ) )
	@SET(__BURST7_PHEBH,0) @" clock cycles
@ENDI
@"
	; Process TCONBURSTCS7 values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__TCONBURSTCS7))
	TCBURST7	EQU	(@__TCONBURSTCS7)
@ELSE
	TCBURST7	EQU	((@__BURST7_PHEBH<<4) | (@__BURST7_PHEBL))
@ENDI
@"
@"
	@"Value definitions for Reset COnfiguration register: RSTCON
@"
	@"Reset Length Control Register (RSTLEN) bitfield: RSTCON.0-2
@IF( ! @DEFINED( __RSTLEN ) )
	@SET(__RSTLEN,0) @" 0 = 16 LCGU clocks
@ENDI			 @" 1 = 32 LCGU clocks
			 @" ... 
			 @" 7 = 2048 LCGU clocks
@"
	@" RSTOUT2 Disable control (RSTOUT2_DIS) bit: RSTCON.7
@IF( ! @DEFINED( __RSTOUT2_DIS ) )
	@SET(__RSTOUT2_DIS,0) @" 0 = RSTOUT2 is activated by any reset trigger
@ENDI			      @" 1 = RSTOUT2 is only activated by hardware reset
@"
	@" RSTOUT Remove (RSTCON_RORMV) bit: RSTCON.4
@IF( ! @DEFINED( __RSTCON_RORMV ) )
	@SET(__RSTCON_RORMV,0) @" 0 = RSTOUT signal is output on pin
@ENDI			      @" 1 = Pin operates as P20.12
@"
	@" RSTOUT signal until einit (RSTCON_ROROFF) bit: RSTCON.5
@IF( ! @DEFINED( __RSTCON_ROROFF ) )
	@SET(__RSTCON_ROROFF,0) @" 0 = RSTOUT is disabled by software or EINIT
@ENDI			      @" 1 = RSTOUT is only disabled by EINIT
@"
	@" RSTOUT Control switching on (RSTCON_ROCON) bit: RSTCON.6
@IF( ! @DEFINED( __RSTCON_ROCON ) )
	@SET(__RSTCON_ROCON,0) @" 0 = RSTOUT is activated on any reset
@ENDI			      @" 1 = RSTOUT2 is only activated by hardware reset
@"
	@" RSTOUT Disable (RSTCON_RODIS) bit: RSTCON.7
@IF( ! @DEFINED( __RSTCON_RODIS ) )
	@SET(__RSTCON_RODIS,0) @" 0 = RSTOUT is controlled by other mechanisms
@ENDI			      @" 1 = RSTOUT2 is deactivated
@"
	; Process RSTCON values
@IF( @DEFINED(@__EXPERT) * @DEFINED(@__RSTCON))
	RSTC		EQU	(@__RSTCON)
@ELSE
	RSTC		EQU	(((@__RSTOUT2_DIS | @__RSTCON_RODIS) <<7) | (@__RSTCON_ROCON << 6) | (@__RSTCON_ROROFF << 5) | (@__RSTCON_RORMV << 4) | (@__RSTLEN))
@ENDI
@"
@"
	@" Value definitions for Watchdog Timer Control Register WDTCON
@IF( @DEFINED( @WDT ) + (@DEFINED(__EXPERT) * @DEFINED(__WDTCON)))
    	@IF( ! @DEFINED( @__WDTIN ) )
		@SET(__WDTIN,1)		@" 0 = frequency = f_CPU/2
	@ENDI				@" 1 = frequency = f_CPU/128
					@" 2 = frequency = f_CPU/4
					@" 3 = frequency = f_CPU/256
	@IF( ! @DEFINED( @__WDTREL ) )
		@SET(__WDTREL,0)	@" Reload value, count up from this
	@ENDI 
@"
	; Process WDTCON values
	@IF( @DEFINED(@__EXPERT) * @DEFINED(@__ADDRSEL2))
		WDT_L		EQU	(LOW @__WDTCON)
		WDT_H		EQU	(HIGH @__WDTCON)
	@ELSE
		WDT_L		EQU		(@__WDTIN)
		WDT_H		EQU		(@__WDTREL)
	@ENDI
		WDT_M_L		EQU		03h	; mask first 2 bits
@ENDI		
@"
@"	
	@" System Stack
	; Stack Size selection of between 32 and 512 words. SYSCON[15..13]
@IF( ! @DEFINED( __STKSZ ) )	@" System stack size
	@SET(__STKSZ, 0)	; 0 = 256 words (Reset value)
@ENDI				@" 1 = 128 words
				@" 2 =  64 words
				@" 3 =  32 words
				@" 4 = 512 words
				@" 7 = No wrapping
@IF( ! @DEFINED(@__SSKTOP) )
	@SET(__SSKTOP,0FC00h)
@ENDI			

@IF( @DEFINED(@__EXPERT) *  @DEFINED(@__SPSEG) )
	@SET(__SSKSEG, @__SPSEG)
@ELSE
	@IF( ! @DEFINED(@__SSKSEG) )
		@SET(__SSKSEG, 00h)
	@ENDI
@ENDI

@IF( ! @DEFINED(@__SSKSIZE) )
	@SET(__SSKSIZE, 256)
@ENDI

@"
@"
;*****************************************************************************
;* __CSTART
;*****************************************************************************
__CSTART_PR	SECTION CODE WORD PUBLIC 'CPROGRAM'
__CSTART 	PROC TASK __CSTART_TASK INTNO __CSTART_INUM = 00H

@IF( @DEFINED( @WDT) + (@DEFINED(@__EXPERT) * @DEFINED(@__WDTCON))) ; Watchdogtimer should be enabled?
	AND	WDTCON, #00FFh		; Yes, set reload value to low
	OR	WDTCON, #1		; set input frequency to low
	SRVWDT				; Enable watchdog
@ELSE
	DISWDT				; No. Disable watchdog timer
@ENDI

	; Set CPUCON1 register.
	MOV	CPUCON1, #(CPC1_L AND CPC1_M_L)

	; Set CPUCON2 register
	MOV	CPUCON2, #((CPC2_L AND CPC2_M_L) OR (CPC2_H AND CPC2_M_H)<<8)

  @IF( @DEFINED( @SYSCON1 ) + (@DEFINED(@__EXPERT) * @DEFINED(@__SYSCON1)))
	EXTR	#01H				; Extended SFR access.
	MOV	SYSCON1, #SYSC1_L		; Set SYSCON1 register.
  @ENDI

  @IF( @DEFINED(@__SYSCON2) * @DEFINED(@__SYSCON3))
@IF( ! @FIXCPU21 )
	EXTR	#02H				; Extended SFR access.
						; Set SYSCON2 register.
	BFLDL	SYSCON2, #SYSC2_M_L, #(SYSC2_L AND SYSC2_M_L)
@ELSE
	EXTR	#03H				; Extended SFR access.
	AND	SYSCON2, #(~(SYSC2_M_L))
	OR	SYSCON2, #(SYSC2_L AND SYSC2_M_L)
@ENDI
	MOV	SYSCON3, #SYSC3			; Set SYSCON3 register.
  @ELSE
      @IF( @DEFINED( @__SYSCON2 ) )
@IF( ! @FIXCPU21 )
	EXTR	#01H				; Extended SFR access.
						; Set SYSCON2 register.
	BFLDL	SYSCON2, #SYSC2_M_L, #(SYSC2_L AND SYSC2_M_L)
@ELSE
	EXTR	#02H				; Extended SFR access.
	AND	SYSCON2, #(~(SYSC2_M_L))
	OR	SYSCON2, #(SYSC2_L AND SYSC2_M_L)
@ENDI
      @ENDI
      @IF( @DEFINED( @__SYSCON3 ) )
	EXTR	#01h				; Extended SFR access.
	MOV	SYSCON3, #SYSC3			; Set SYSCON3 register.
      @ENDI
  @ENDI

  @IF(@DEFINED( @PLLCON ) + (@DEFINED(@__EXPERT)*@DEFINED(@__PLLCON)))
	EXTR	#01h
	MOV	PLLCON, #PLLC			; Set PLLCON register
  @ENDI

	@_MOVE	(EBCMOD0, #EBC0, R0)		; Set EBCMOD0 register

  @IF( @DEFINED( @LNDCS0 ) )
	@IF( @__ACTIVE_TCONBURSTCS0 )
	    @_MOVE (TCONBURSTCS0, #TCBURST0, R0) ; Set TCONBURSTCS0 register
	@ENDI
	@_MOVE 	(FCONCS0, #FCS0, R0)		; Set FCONCS0 register
	@_MOVE	(TCONCS0, #TCS0, R0)		; Set TCONCS0 register
  @ENDI

  @IF( @DEFINED( @LNDCS1 )  + (@DEFINED(@__EXPERT)*(@DEFINED(@__FCONCS1)+@DEFINED(@__TCONCS1)+@DEFINED(@__ADDRSEL1))))
	@IF( @__ACTIVE_TCONBURSTCS1 )
	    @_MOVE (TCONBURSTCS1, #TCBURST1, R0) ; Set TCONBURSTCS1 register
	@ENDI
	@_MOVE	(ADDRSEL1, #ADRS1, R0)		; Set ADDRSEL1 register
	@_MOVE 	(TCONCS1, #TCS1, R0)		; Set TCONCS1 register
	@_MOVE 	(FCONCS1, #FCS1, R0)		; Set FCONCS1 register
  @ENDI

  @IF( @DEFINED( @LNDCS2 ) + (@DEFINED(@__EXPERT)*(@DEFINED(@__FCONCS2)+@DEFINED(@__TCONCS2)+@DEFINED(@__ADDRSEL2))))
	@IF( @__ACTIVE_TCONBURSTCS2 )
	    @_MOVE (TCONBURSTCS2, #TCBURST2, R0) ; Set TCONBURSTCS2 register
	@ENDI
	@_MOVE	(ADDRSEL2, #ADRS2, R0)		; Set ADDRSEL2 register
	@_MOVE 	(TCONCS2, #TCS2, R0)		; Set TCONCS2 register
	@_MOVE 	(FCONCS2, #FCS2, R0)		; Set FCONCS2 register
  @ENDI

  @IF( @DEFINED( @LNDCS3 )  + (@DEFINED(@__EXPERT)*(@DEFINED(@__FCONCS3)+@DEFINED(@__TCONCS3)+@DEFINED(@__ADDRSEL3))))
	@IF( @__ACTIVE_TCONBURSTCS3 )
	    @_MOVE (TCONBURSTCS3, #TCBURST3, R0) ; Set TCONBURSTCS3 register
	@ENDI
	@_MOVE	(ADDRSEL3, #ADRS3, R0)		; Set ADDRSEL3 register
	@_MOVE 	(TCONCS3, #TCS3, R0)		; Set TCONCS3 register
	@_MOVE 	(FCONCS3, #FCS3, R0)		; Set FCONCS3 register
  @ENDI

  @IF( @DEFINED( @LNDCS4 )  + (@DEFINED(@__EXPERT)*(@DEFINED(@__FCONCS4)+@DEFINED(@__TCONCS4)+@DEFINED(@__ADDRSEL4))))
	@IF( @__ACTIVE_TCONBURSTCS4 )
	    @_MOVE (TCONBURSTCS4, #TCBURST4, R0) ; Set TCONBURSTCS4 register
	@ENDI
	@_MOVE	(ADDRSEL4, #ADRS4, R0)		; Set ADDRSEL4 register
	@_MOVE 	(TCONCS4, #TCS4, R0)		; Set TCONCS4 register
	@_MOVE 	(FCONCS4, #FCS4, R0)		; Set FCONCS4 register
  @ENDI

  @IF( @DEFINED( @LNDCS5 )  + (@DEFINED(@__EXPERT)*(@DEFINED(@__FCONCS5)+@DEFINED(@__TCONCS5)+@DEFINED(@__ADDRSEL5))))
	@IF( @__ACTIVE_TCONBURSTCS5 )
	    @_MOVE (TCONBURSTCS5, #TCBURST5, R0) ; Set TCONBURSTCS5 register
	@ENDI
	@_MOVE	(ADDRSEL5, #ADRS5, R0)		; Set ADDRSEL5 register
	@_MOVE 	(TCONCS5, #TCS5, R0)		; Set TCONCS5 register
	@_MOVE 	(FCONCS5, #FCS5, R0)		; Set FCONCS5 register
  @ENDI

  @IF( @DEFINED( @LNDCS6 )  + (@DEFINED(@__EXPERT)*(@DEFINED(@__FCONCS6)+@DEFINED(@__TCONCS6)+@DEFINED(@__ADDRSEL6))))
	@IF( @__ACTIVE_TCONBURSTCS6 )
	    @_MOVE (TCONBURSTCS6, #TCBURST6, R0) ; Set TCONBURSTCS6 register
	@ENDI
	@_MOVE	(ADDRSEL6, #ADRS6, R0)		; Set ADDRSEL6 register
	@_MOVE 	(TCONCS6, #TCS6, R0)		; Set TCONCS6 register
	@_MOVE 	(FCONCS6, #FCS6, R0)		; Set FCONCS6 register
  @ENDI

  @IF( @DEFINED( @LNDCS7 )  + (@DEFINED(@__EXPERT)*(@DEFINED(@__FCONCS7)+@DEFINED(@__TCONCS7)+@DEFINED(@__ADDRSEL7))))
	@IF( @__ACTIVE_TCONBURSTCS7 )
	    @_MOVE (TCONBURSTCS7, #TCBURST7, R0) ; Set TCONBURSTCS7 register
	@ENDI
	@_MOVE	(ADDRSEL7, #ADRS7, R0)		; Set ADDRSEL7 register
	@_MOVE 	(TCONCS7, #TCS7, R0)		; Set TCONCS7 register
	@_MOVE 	(FCONCS7, #FCS7, R0)		; Set FCONCS7 register
  @ENDI

  @IF( @DEFINED( @RSTCON ) + (@DEFINED(@__EXPERT)*(@DEFINED(@__RSTCON))))
	@_MOVE(RSTCON, #RSTC, R0)		; set RSTCON using long addressing mode
  @ENDI

	MOV	STKOV,	#SOF ?SYSSTACK_BOTTOM + 6*2	; Set stack overflow pointer.
	MOV	SP,	#SOF ?SYSSTACK_TOP		; Set stack pointer.
	MOV	STKUN,	#SOF ?SYSSTACK_TOP		; Set stack underflow pointer.
  @IF( @DEFINED( @SSKENABLE) + (@DEFINED(@__EXPERT)*@DEFINED(@__SPSEG)))
	MOV	SPSEG,	#@__SSKSEG			; Set stack segment
  @ENDI

	MOV	CP, 	#CSTART_RBANK		; Set context pointer.
	NOP			

  @IF( @EQS(@MODEL,"MEDIUM") | @EQS(@MODEL,"LARGE") )
	MOV	DPP1, #PAG C166_XGROUP			; set DPP1 to page of user stack / xnear data
	MOV	R0, #POF (?USRSTACK_TOP - 2) + 04002h	; set user stack pointer
  @ELSE
	MOV	DPP0, #PAG ?BASE_DPP0	; Set data page pointer.
	MOV	DPP1, #PAG ?BASE_DPP1	; Initialise these before we can make a
	MOV	DPP2, #PAG ?BASE_DPP2	; user stack call below
	MOV	R0, #?USRSTACK_TOP	; set user stack pointer
  @ENDI

@IF( ! @FIXCPU21 )
	BFLDH	PSW, #3, #2		; set local register bank 0 (10)
@ELSE
	BSET	PSW.9			; set local register bank 0 (10)
@ENDI
  @IF( @EQS(@MODEL,"MEDIUM") | @EQS(@MODEL,"LARGE") )
	MOV	R0, #POF (?USRSTACK0_TOP - 2) + 04002h	; set user stack pointer
  @ELSE
	MOV	R0, #?USRSTACK0_TOP	; set user stack pointer
  @ENDI
	
@IF( ! @FIXCPU21 )
	BFLDH	PSW, #3, #3		; set local register bank 1 (11)
@ELSE
	OR	PSW, #00300h		; set local register bank 1 (11)
@ENDI
  @IF( @EQS(@MODEL,"MEDIUM") | @EQS(@MODEL,"LARGE") )
	MOV	R0, #POF (?USRSTACK1_TOP - 2) + 04002h	; set user stack pointer
  @ELSE
	MOV	R0, #?USRSTACK1_TOP	; set user stack pointer
  @ENDI
	
@IF( @_EXT22 )
    @IF( ! @FIXCPU21 )
	BFLDH	PSW, #3, #1		; set local register bank 2 (01)
    @ELSE
	BCLR	PSW.9			; set local register bank 2 (01)
    @ENDI
  @IF( @EQS(@MODEL,"MEDIUM") | @EQS(@MODEL,"LARGE") )
	MOV	R0, #POF (?USRSTACK2_TOP - 2) + 04002h	; set user stack pointer
  @ELSE
	MOV	R0, #?USRSTACK2_TOP	; set user stack pointer
  @ENDI
@ENDI

@IF( ! @FIXCPU21 )
	BFLDH	PSW, #3, #0		; set to global user stack
@ELSE
	AND	PSW, #0FCFFh		; set to global user stack
@ENDI
		
@IF( @DEFINED( @CALLEINIT))
@_SERVWDT
  @"Initialise remaining DPP's to allow the use of near C variables. However, if
  @" variables are initialised or cleared, the _c_init will override these values
  @" anyway
  @IF( @EQS(@MODEL,"MEDIUM") | @EQS(@MODEL,"LARGE") )
    	MOV 	DPP0, #0			; restore DPP0 to its default value
	MOV	DPP2, #PAG C166_DGROUP		; set DPP2 to page of default data 
  @ENDI
@_CALL( @CALLEINIT, R1)		
@ENDI
; by Wilhelm !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;EXTR	#01h				; Extended SFR access.
;MOV	SYSCON3, #0h	   ; alle Peripherals aktivieren
; end by Wilhelm !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
	EINIT				; End of initialization

; start of init function
@_CALL(__C_INIT, R1)		
; end of init function

  @IF( @EVA )
        BSET    IEN                     ; allow monitor to break application
  @ENDI
 
        MOV     R12, #0                 ; set argc to 0
        MOV     R13, #0                 ;
        MOV     R14, #0                 ; set argv[] to 0

;
; Set the watchdog timer to the user defined values at this point.
;
@IF( @DEFINED( @WDT) )			; If watchdogtimer enabled
@IF( ! @FIXCPU21 )
	BFLDH	WDTCON, #0FFh, #WDT_H	; set reload value
	BFLDL	WDTCON, #WDT_M_L, #(WDT_L AND WDT_M_L) ; set input frequency
@ELSE
	AND	WDTCON, #(~(WDT_M_L))
	OR	WDTCON, #(WDT_H << 8 OR (WDT_L AND WDT_M_L))
@ENDI
	@_SERVWDT			; Service Watchdog Timer (if enabled)
@ENDI


@IF( @DEFINED( @CALLINIT))
@_CALL( @CALLINIT, R1)		
@_SERVWDT				; Service Watchdog Timer (if enabled)
@ENDI


@_CALL( _main, R1)

; The exit() function causes normal program termination to occur. First, all 
; functions registered by the atexit() function are called in the reverse 
; order. Next, all open streams with unwritten buffered data are flushed, all 
; open streams are closed and all files created by the tmpfile() function are 
; removed. The status value passed to exit is returned in R4.
__EXIT: LABEL FAR			; the exit() or abort() function jumps
					; to this entry.

	@_SERVWDT			; Service Watchdog Timer (if enabled)

@IF( @EX_AB )
					; restore (host) environment.
	MOV	SP, #SOF ?SYSSTACK_TOP	; restore stack pointer.
  @IF( @EQS(@MODEL,"MEDIUM") | @EQS(@MODEL,"LARGE") )
	MOV	R0, #POF (?USRSTACK_TOP	- 2) + 04002h ; restore user stack pointer
  @ELSE
	MOV	R0, #?USRSTACK_TOP	; restore user stack pointer
  @ENDI
@ENDI

__IDLE: IDLE				; Power down CPU until peripheral inter-
					; rupt or external interrupt occurs.
	JMPR	CC_UC, __IDLE		; set idle mode again.
	RETV				; Virtual return.
__CSTART	ENDP
__CSTART_PR	ENDS

@IF( @EQS(@MODEL,"TINY") | @EQS(@MODEL,"SMALL") )
C166_US	SECTION	LDAT WORD GLBUSRSTACK 'CUSTACK'
@ENDI
@IF( @EQS(@MODEL,"MEDIUM") | @EQS(@MODEL,"LARGE") )
C166_US	SECTION	DATA WORD GLBUSRSTACK 'CUSTACK'
@ENDI
@IF( @_USRSTACK & ( @EQS(@MODEL,"SMALL") | @EQS(@MODEL,"LARGE") ) )
  @IF( @EQS( @MODEL, "SMALL" ) | @EQS( @MODEL, "LARGE" ) )
	DS	2+4		; Allocate a user stack of at least 2 bytes +
				; return label main (__MAIN_RET).
  @ELSE
	DS	2+2		; Allocate a user stack of at least 2 bytes +
				; return label main (__MAIN_RET).
  @ENDI
@ELSE
	DS	2		; Allocate a user stack of at least 2 bytes
@ENDI
C166_US	ENDS

; Define empty user stack used with localregister bank 0.
@IF( @EQS(@MODEL,"TINY") | @EQS(@MODEL,"SMALL") )
C166_US0 SECTION LDAT WORD GLBUSRSTACK 'CUSTACK'
@ENDI
@IF( @EQS(@MODEL,"MEDIUM") | @EQS(@MODEL,"LARGE") )
C166_US0 SECTION DATA WORD GLBUSRSTACK 'CUSTACK'
@ENDI
C166_US0 ENDS

; Define empty user stack used with localregister bank 1.
@IF( @EQS(@MODEL,"TINY") | @EQS(@MODEL,"SMALL") )
C166_US1 SECTION LDAT WORD GLBUSRSTACK 'CUSTACK'
@ENDI
@IF( @EQS(@MODEL,"MEDIUM") | @EQS(@MODEL,"LARGE") )
C166_US1 SECTION DATA WORD GLBUSRSTACK 'CUSTACK'
@ENDI
C166_US1 ENDS

; Define empty user stack used with localregister bank 2.
@IF( @EQS(@MODEL,"TINY") | @EQS(@MODEL,"SMALL") )
C166_US2 SECTION LDAT WORD GLBUSRSTACK 'CUSTACK'
@ENDI
@IF( @EQS(@MODEL,"MEDIUM") | @EQS(@MODEL,"LARGE") )
C166_US2 SECTION DATA WORD GLBUSRSTACK 'CUSTACK'
@ENDI
C166_US2 ENDS

@IF( @EQS(@MODEL,"MEDIUM") | @EQS(@MODEL,"LARGE") )
C166_DGROUP	DGROUP	__DUMMY
__DUMMY	SECTION DATA WORD PUBLIC 'CNEAR'
__DUMMY	ENDS
C166_XGROUP	DGROUP	__XDUMMY,C166_US,C166_US0,C166_US1
__XDUMMY SECTION DATA WORD PUBLIC
__XDUMMY ENDS
@ENDI

@IF( @DEFINED(@SSKENABLE) )
C166_SYSSTACK SECTION HDAT WORD SYSSTACK
	DS @__SSKSIZE * 2		; Reserve stack size in words
C166_SYSSTACK ENDS

		SSKDEF 7		; System stack size
@ELSE
		SSKDEF	@__STKSZ	; System stack size
@ENDI

CSTART_RBANK	REGDEF R0-R15		; Register usage
	
@IF( @DEFINED( @CALLNUCLEUS))
$include(int_166.asm)                   ; include Nucleus assembly startup file
                                        ; containing _main label entry point 
@ENDI

@IF( @DEFINED( @CALL_USER))
$include( @CALL_USER )                  ; include user defined assembly 
					; startup file containing _main label 
					; entry point 
@ENDI
	
	END